Write Assist Circuitry for Memory Voltage Drop Reduction
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Solution Overview
Problem
In newer generation memory devices, the increased resistance in bit-lines and complementary bit-lines makes it challenging to effectively transfer negative voltages during write cycles, leading to voltage drops that adversely affect write performance.
Innovation Solution
The use of a p-type metal-oxide-semiconductor (PMOS) transistor to couple bit-lines or complementary bit-lines to a voltage rail during write cycles, in conjunction with n-type metal-oxide-semiconductor (NMOS) transistors, reduces voltage drops by allowing a positive voltage to be applied with less drop, and a multiplexer circuit to manage voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If NMOS transistors are used to couple bit-lines to write drive inputs during write cycles, then write drive capability is improved, but voltage drops increase due to increased resistance in bit-lines
Solution Approach 1:
The patent combines NMOS transistors for write drive capability with PMOS transistors in multiplexer circuits to supply voltage rails, creating a hybrid approach that leverages the complementary strengths of both transistor types to achieve both strong write drive and reduced voltage drops
Solution Approach 2:
The PMOS transistor in the multiplexer circuit acts as an intermediary between the voltage rail and the bit-line, providing a controlled voltage path that reduces voltage drops during write cycles while maintaining write drive capability through the NMOS transistor
2Ease of manufacture
If bit-line resistance is increased, then manufacturing is simplified, but write performance deteriorates due to voltage drops
Solution Approach 1:
The patent changes the voltage parameter by introducing a voltage rail coupled through a PMOS transistor, which modifies the voltage profile along the bit-line during write cycles, thereby compensating for increased resistance without compromising write performance
3Loss of energy
If PMOS transistors are added to couple bit-lines to voltage rails, then voltage drops are reduced, but device complexity increases
Solution Approach 1:
The PMOS transistor in the multiplexer circuit serves multiple functions: it acts as a voltage switch, a protection element, and a voltage regulation component, thereby reducing voltage drops while minimizing the need for additional separate circuits
Data Source
AI summary
Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.