Memory Device Write Signal Generation Circuit
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Solution Overview
Problem
Existing memory devices face challenges in efficiently writing data to bit cells while protecting data stored in other cells, particularly due to signal racing issues and crowbar currents.
Innovation Solution
The memory device incorporates a main I/O circuit and a local I/O circuit that generate global and local write signals, respectively, to manage data writing and bit write masking, avoiding signal racing and crowbar currents by operating within the same time domain as the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write operations are used to write data to bit cells, then data writing speed is improved, but signal racing and crowbar currents occur causing unintended data changes
Solution Approach 1:
The patent divides the write operation into two distinct phases: a first write operation that writes to a first bit cell, and a second write operation that writes to a second bit cell. This segmentation ensures that write operations to different bit cells are separated in time, preventing signal racing and crowbar currents that would occur in conventional simultaneous write operations, thereby maintaining data storage reliability while achieving high productivity through pipelined operations.
2Reliability
If bit write masking is implemented to protect stored data, then data protection is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic bit write masking where the masking state is controlled by a write mask signal that can be changed during operation. The circuit transitions between masked and unmasked states based on the write mask signal, allowing flexible data protection only when needed. This dynamic approach provides effective data protection while minimizing device complexity by using simple signal-controlled switching rather than permanent complex masking circuitry.
Data Source
AI summary
A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.