Semiconductor Memory Initialization Signal Generation Circuit
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Solution Overview
Problem
Semiconductor memory devices face challenges in accurately setting the level change time point of initialization signals due to PVT variations, leading to incomplete auto refresh operations and imprecise termination of the initialization mode.
Innovation Solution
An initialization signal generation circuit is introduced, comprising a flag signal generator, an auto refresh signal generator, and an initialization signal generator, which includes a counter unit to delay the counting initialization signal based on the refresh counting signal, ensuring accurate timing even with varying pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the preliminary refresh signal AREF_PRE has a large pulse width due to PVT variation, then the pulse of the counting initialization signal INIT_CNT may overlap with the pulse of the preliminary refresh signal, but this causes the initialization signal DAI to be disabled at an incorrect time point within the auto refresh period
Solution Approach 1:
The patent introduces a delay signal generation circuit that generates a delay signal based on the falling edge of the preliminary refresh signal AREF_PRE. This delay signal serves as an intermediary to accurately control the timing of the initialization signal DAI, preventing incorrect disabling due to pulse overlap while maintaining reliable initialization operations
Solution Approach 2:
The patent generates the delay signal in advance based on the falling edge of the preliminary refresh signal before the potential overlap occurs. This preliminary timing action ensures that the initialization signal is disabled at the correct time point, preventing the harmful effect of incorrect timing while maintaining system reliability
2Productivity
If the initialization operation is terminated within 10 us for LPDDR2 memory devices, then the performance requirement is met, but the auto refresh operation may not be performed sufficiently to the preset level
Solution Approach 1:
The patent uses the delay signal generated from the falling edge of the preliminary refresh signal as a feedback mechanism to monitor and control the initialization operation timing. This feedback ensures that the initialization signal is disabled only after sufficient auto refresh operations are completed, maintaining both speed and reliability
Solution Approach 2:
The patent dynamically adjusts the timing of the initialization signal disabling based on the actual pulse width and timing of the preliminary refresh signal. This dynamic timing adjustment allows the system to meet the 10 us performance requirement while ensuring sufficient auto refresh operations are performed
Data Source
AI summary
An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination.