ECC Circuit Per Symbol Error Correction for Memory Devices
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Solution Overview
Problem
As semiconductor memory devices become smaller in size, the bit error rate (BER) of memory cells increases, necessitating enhanced error correction capabilities to maintain data integrity.
Innovation Solution
A semiconductor memory device incorporating an error correcting code (ECC) circuit that generates parity data, writes codewords, reads syndromes, and corrects errors on a per symbol basis for adjacent memory cells, reducing the number of required parity or check bits by correcting one or two errors per symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory device size is reduced, then the device becomes smaller and more integrated, but the bit error rate increases
Solution Approach 1:
The patent applies preliminary action by generating parity data and creating codewords before data is stored in the memory device. The ECC circuit pre-processes the main data by generating q-bit parity data through encoding, then combines it with 2p-bit main data to form codewords that are stored in the memory cell array. This preliminary error correction preparation allows the system to detect and correct errors that occur during storage without requiring larger device size.
Solution Approach 2:
The patent introduces an intermediary error correction code circuit that mediates between the main data and the memory storage system. The ECC circuit generates syndromes by comparing the stored codeword with regenerated check bits, acting as an intermediary layer that identifies and corrects errors before they affect the actual data integrity. This intermediary mechanism enables reliable data storage in smaller memory devices with higher error rates.
2Reliability
If more parity bits are added to correct errors, then error correction capability improves, but the number of required parity or check bits increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction task into segments handled at different levels. The ECC circuit segments the codeword into 2p-bit main data and q-bit parity data, where q > p. The decoder then segments the error correction process into syndrome generation (comparing check bits with parity data) and error identification phases. This segmentation allows efficient error correction with minimized parity bits by focusing correction efforts only where errors are detected.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the syndrome values based on the comparison between check bits and parity data. The syndrome generator changes the parameter values of syndromes according to the error patterns detected, allowing the system to adapt the correction process to the actual error conditions. This parameter-based approach enables effective error correction with fewer parity bits compared to fixed redundancy schemes.
Data Source
AI summary
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.