Memory Array Data Inversion for Soft Error Reduction
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Solution Overview
Problem
Semiconductor memory devices, such as DRAMs, are susceptible to non-defect related errors like soft errors due to noise and radiation, which can lead to data loss and increased circuit complexity, power usage, and reduced access time, and latent defects can further increase signal loss and soft error rates.
Innovation Solution
The method involves configuring a memory array to store data in a preferred bias condition, where a majority of memory cells store internal data values in a preferred state, typically '0', opposite to the external data state, to reduce the impact of noise and soft errors, and selectively inverting data on write and read paths to make stored values independent of memory cell location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques are implemented to correct data loss from soft errors, then data reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent inverts the conventional approach by proactively storing data in the opposite state of its natural bias condition. Instead of correcting errors after they occur, the system prevents soft errors by storing '0' as '1' and '1' as '0' in memory cells, thereby reducing the impact of random electrical occurrences that cause state changes.
Solution Approach 2:
The patent performs preliminary data inversion before storing data in memory cells. By anticipating the bias condition of memory cells and pre-inverting data accordingly, the system prepares data in advance to counteract potential soft errors, eliminating the need for complex error correction circuits.
2Reliability
If error correction techniques are implemented to correct data loss from soft errors, then data reliability is improved, but power usage increases
Solution Approach 1:
The patent inverts the conventional approach by proactively storing data in the opposite state of its natural bias condition. Instead of correcting errors after they occur, the system prevents soft errors by storing '0' as '1' and '1' as '0' in memory cells, thereby reducing the impact of random electrical occurrences that cause state changes.
Solution Approach 2:
The patent extracts and eliminates the need for power-consuming error correction circuits by using a simpler preventive approach. Data inversion is performed using existing memory cell bias conditions without requiring additional error detection and correction hardware, thereby reducing power usage.
3Reliability
If error correction techniques are implemented to correct data loss from soft errors, then data reliability is improved, but access time increases
Solution Approach 1:
The patent performs preliminary data inversion before storing data in memory cells. By anticipating the bias condition of memory cells and pre-inverting data accordingly, the system prepares data in advance to counteract potential soft errors, eliminating the need for complex error correction circuits.
Solution Approach 2:
The patent extracts and eliminates the need for power-consuming error correction circuits by using a simpler preventive approach. Data inversion is performed using existing memory cell bias conditions without requiring additional error detection and correction hardware, thereby reducing power usage.
4Productivity
If memory array density is increased to improve storage capacity, then productivity is improved, but susceptibility to noise and soft errors increases
Solution Approach 1:
The patent applies local quality by tailoring the data storage state to the specific characteristics of each memory cell's location and bias condition. Memory cells are grouped into sets with different bias conditions, and data is inverted differently for each set, optimizing each local region's resistance to noise and soft errors.
Data Source
AI summary
A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.