Computational Memory Storage Array Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies as dual port SRAM cells are larger than high-density memories, making it inefficient to store data in computational memory cells, which are also used for logic operations, limiting their capacity for complex computations and data storage.
Innovation Solution
A processing array with an array of computational dual port SRAM cells connected to a storage array, utilizing error checking circuitry and multiplexers to perform complex logic functions and store data efficiently, allowing for operations like XOR and XNOR computations while minimizing cell size limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual port SRAM cells are used for computational memory operations, then logic computation capability is improved, but storage capacity deteriorates due to larger cell size compared to high-density memories
Solution Approach 1:
The system is divided into two distinct segments: computational memory cells (dual port SRAM) dedicated to logic operations, and separate high-density storage cells for data retention. This segmentation allows each component to be optimized for its specific function without compromise
Solution Approach 2:
The dual port SRAM cells serve multiple functions: they act as both computational units for logic operations and as temporary storage registers. The separate high-density memory provides universal data storage capability, creating a multi-functional memory system
2Quantity of substance
If dual port SRAM cells are used to store data, then data storage is enabled, but efficiency deteriorates due to significantly larger cell size
Solution Approach 1:
The memory system is segmented into computational SRAM cells and separate high-density storage cells. The storage cells handle data retention while the SRAM cells handle computation, optimizing both functions independently
Solution Approach 2:
The dual port SRAM cells act as intermediary structures between the high-density storage and the computational logic. They temporarily hold data during computation and facilitate efficient data transfer without requiring the high-density storage to directly participate in logic operations
3Adaptability or versatility
If computational memory cells are used for both computation and storage, then functionality is improved, but cell size limitations worsen processing capabilities
Solution Approach 1:
The system separates computation and storage into different physical structures with different cell sizes. High-density storage cells handle data retention while smaller computational SRAM cells handle logic operations, eliminating the cell size bottleneck for computation
Solution Approach 2:
The architecture adds a temporal dimension to data handling by using the dual port SRAM as a buffer between storage and computation. Data moves from high-density storage to SRAM for processing, then back to storage, creating a multi-stage data flow that overcomes cell size limitations
Data Source
AI summary
A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.