Memory Device Word Line Precharge for Sensing Margin
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Solution Overview
Problem
Resistive memory devices face challenges in maintaining sensing margin and reducing read disturb characteristics due to parasitic capacitor components and capacitance differences between layers in three-dimensional cross-point structures.
Innovation Solution
A memory device and operating method that include a memory cell array with a precharge operation controlled by row and column decoders, where a selected word line is weakly turned on during the bit line precharge period to increase sensing margin and compensate for capacitance differences between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a constant current or voltage is applied to sense data in memory cells, then data can be read by measuring voltage variation, but parasitic capacitor components on word lines and bit lines cause sensing margin degradation and read disturb
Solution Approach 1:
The patent applies preliminary precharge operations to word lines and bit lines before the actual sensing operation. By precharging the parasitic capacitors to known voltage levels beforehand, the sensing operation can accurately measure only the resistance-induced voltage changes without being affected by unknown initial capacitor states, thereby improving sensing margin
Solution Approach 2:
The patent introduces dummy memory cells connected to the same bit lines as real memory cells. These dummy cells serve as intermediaries to compensate for bit line parasitic capacitance effects. By sensing the voltage on dummy cells and comparing it with real cell voltages, the system can eliminate the influence of parasitic capacitors on the measurement accuracy
2Quantity of substance
If first and second layers are stacked vertically sharing bit lines in a three-dimensional cross point structure, then memory density increases, but capacitance differences between layers cause different sensing margin and read disturb characteristics
Solution Approach 1:
The patent applies different precharge voltages to word lines in different layers. Specifically, first word lines in the first layer are precharged to a first voltage level while second word lines in the second layer are precharged to a second voltage level. This local differentiation compensates for the capacitance differences between layers, ensuring that each layer experiences appropriate precharge conditions for reliable sensing
Solution Approach 2:
The patent changes the precharge voltage parameter for different layers to compensate for capacitance variations. By adjusting the precharge voltage levels (first voltage for first layer, second voltage for second layer), the system optimizes the sensing conditions for each layer, maintaining consistent sensing margin and read disturb characteristics across layers despite their different parasitic capacitances
Data Source
AI summary
A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.