Non-Volatile Memory Row Data Buffer Relocation for Speed
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in reducing memory area and achieving high-speed operations due to the placement of Row Data Buffers within the bank, which increases the distance to the DQ pad and slows down read/write operations.
Innovation Solution
A Low Power Double Data Rate (LPDDR) 2 specification-based non-volatile memory device with a Row Data Buffer (RDB) array positioned adjacent to the DQ pad, reducing memory area and shortening the read/write path length by integrating a data input/output unit that includes a register, data transmitting unit, data storing unit, and data input buffer to facilitate high-speed data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Row Data Buffer is placed within the bank, then data buffering function is achieved, but the distance to the DQ pad increases and operation speed decreases
Solution Approach 1:
The patent extracts the Row Data Buffer from the bank structure and relocates it to the periphery of the cell array, adjacent to the DQ pad. This separation allows the buffer to perform its data buffering function independently while minimizing the access path length to the pad, thereby resolving the contradiction between maintaining buffering functionality and achieving high-speed operations.
2Reliability
If the Row Data Buffer is placed within the bank, then data buffering is provided, but the memory area increases
Solution Approach 1:
By extracting the Row Data Buffer from the bank area and positioning it in the periphery region adjacent to the DQ pad, the patent reduces the area occupied within the cell array. This spatial reorganization maintains the necessary data buffering capacity while minimizing the overall memory footprint.
3Speed
If the access path length is reduced, then operation speed increases, but the data buffering capacity may be compromised
Solution Approach 1:
The patent positions the Row Data Buffer as an intermediary component between the cell array and the DQ pad. This mediator role allows the buffer to maintain adequate data buffering capacity while being located adjacent to the pad, thus achieving both high-speed data access and sufficient buffering functionality simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for faster read and write operations by curtailed access paths and reduces memory area, improving data access speed and reducing the impact of temperature variations on data integrity.
Implementation Method 1
the phase change material layer 2 whose phase is inter-changeable between a crystalline phase and an amorphous phase depending on the temperature applied to the GST
Implementation Method 2
If a voltage and current are applied to the top electrode 1 and the bottom electrode 3, a current signal and a high temperature are provided to the PCM layer 2
Data Source
AI summary
A non-volatile memory device includes a bank including a plurality of unit cells so as to output sensed data to a global input/output (I/O) line, and a data input/output (I/O) unit configured to store the same data as that of a unit cell contained in a bank in a register, store external input data in the register during a write operation, and output data stored in the register to an external part during a read operation.