Stacked Memory Partitioned Data Bus Bandwidth
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Solution Overview
Problem
Conventional memory devices with stacked memory device dice face limitations in achieving high data rate and bandwidth without significant cost increases, due to rank-to-rank turnaround overhead and inefficient channel utilization.
Innovation Solution
The implementation of a stacked memory device configuration with partitioned data and control/address buses, utilizing multiplexers and transceivers to deliver bandwidth over single data channels in a point-to-point configuration, eliminating rank-to-rank turnaround overhead and enhancing channel utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stacked memory device configuration is used with multiple data channels, then memory capacity is increased, but bandwidth efficiency deteriorates due to rank-to-rank turnaround overhead
Solution Approach 1:
The memory device is segmented into two separate memory stacks, where each stack has its own dedicated data channel. This segmentation eliminates the need for rank-to-rank turnaround overhead by allowing independent parallel access to both stacks, thereby improving bandwidth efficiency while maintaining increased memory capacity.
2Productivity
If more data channels are added to increase bandwidth, then data rate is improved, but device complexity increases
Solution Approach 1:
Two memory stacks are merged into a single memory device package with a unified interface architecture. Each stack operates independently with its own data channel, but both channels are managed through a single memory device interface, reducing overall system complexity while achieving doubled bandwidth through parallel operation.
3Quantity of substance
If stacked memory device configuration is implemented, then memory density is increased, but channel utilization efficiency deteriorates
Solution Approach 1:
The memory architecture transitions from a single-plane vertical stack to a two-stack parallel configuration. By adding the dimension of parallel stack operation with dedicated data channels, the system achieves high memory density while maintaining efficient channel utilization, as each channel operates independently without contention.
Data Source
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AI summary
Apparatus and methods of increasing the data rate and bandwidth of system memory including stacked memory device dice. The system memory includes a memory device having a plurality of memory device dice in a stacked configuration, a memory controller coupled to the stacked memory device dice, and a partitioned data bus. The memory device dice each include one, two, or more groups of memory banks. By configuring each memory device die to deliver all of its bandwidth over a different single partition of the data channel, the system memory can achieve an increased data rate and bandwidth without significantly increasing costs over typical system memory configurations that include stacked memory device dice.