Memory Cell Layout Reducing Unit Area via Alternate Gate Coupling
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Solution Overview
Problem
Existing non-volatile memory devices with polysilicon gate electrodes require a silicide blocking layer to enhance charge retention, which increases the unit area of memory cells, limiting their density and efficiency.
Innovation Solution
The implementation of an alternate gate coupling arrangement in memory array layouts, where the second capacitor plate is larger than the gate electrode, allowing for more precise charge storage and reducing the unit area of memory cells from 4.4 um2 to 3.3 um2 by optimizing the layout and interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicide blocking layer is added to enhance charge retention in polysilicon gate electrodes, then charge retention is improved, but the unit area of memory cells increases
Solution Approach 1:
The patent removes the silicide blocking layer from the memory cell structure, extracting the problematic component that was causing area expansion. Instead of adding the blocking layer to improve charge retention, the invention finds an alternative approach that achieves reliable charge storage without this area-increasing layer, thereby resolving the contradiction between charge retention and memory cell area
Solution Approach 2:
The patent changes the size parameter of the second capacitor plate, making it larger than the gate electrode area. This parameter change allows the capacitor to store sufficient charge without requiring the silicide blocking layer, thus maintaining charge retention while reducing the overall memory cell area
2Measurement precision
If the second capacitor plate is made larger than the gate electrode, then charge storage precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the capacitor structure with the transistor gate structure by making the second capacitor plate larger than and overlapping with the gate electrode. This merging of structures achieves precise charge storage while actually simplifying the layout by reducing the number of separate components and their associated interconnects, thus resolving the apparent contradiction between precision and complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the unit area of memory cells, improving density and reducing charge storage variations, while maintaining compatibility with standard CMOS logic processes and avoiding misalignment issues, thus enhancing the performance and efficiency of memory devices.
Implementation Method 1
a capacitor including first and second capacitor plates separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region
Data Source
AI summary
Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.