Pulsed Sub-VDD Bit Line Precharging for Memory Access Optimization
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Solution Overview
Problem
The bit line pre-charge operation in memory arrays affects access times, as it may not be adequately charged in time for high-speed read operations or overcharged for low-speed operations, impacting both performance and power consumption.
Innovation Solution
A pre-charge circuit that charges the true and complement bit lines to a voltage level less than the power supply signal for a short duration and maintains this level using a second current source to prevent overcharging, allowing for efficient and rapid pre-charging across varying access rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line is charged to the full power supply voltage level for a long duration, then the bit line is adequately charged for high-speed read operations, but the bit line becomes overcharged for low-speed operations resulting in increased power consumption
Solution Approach 1:
The patent changes the voltage parameter by charging the bit line to a reduced voltage level (less than the full power supply voltage) during the pre-charge phase. This parameter modification allows the bit line to be sufficiently charged for high-speed operations while preventing overcharging and excessive power consumption during low-speed operations.
Solution Approach 2:
The patent employs periodic pulsed pre-charge operations where the bit line is charged in controlled pulses rather than continuously. This periodic action enables precise control over the charging duration and voltage level, allowing the system to adapt to varying operation speeds and minimize power consumption while maintaining adequate charge levels.
2Reliability
If the bit line pre-charge duration is extended to ensure adequate charging, then high-speed read operations are supported, but access time increases for low-speed operations
Solution Approach 1:
The patent performs preliminary charging of the bit line to an intermediate voltage level before the actual read operation. This preliminary action ensures that the bit line is partially charged in advance, reducing the additional charging time required during the read operation itself, thereby maintaining reliability while minimizing total access time.
Solution Approach 2:
The patent implements dynamic control of the pre-charge circuit based on the anticipated operation speed. The pre-charge duration and voltage level are dynamically adjusted according to whether high-speed or low-speed operations are expected, allowing the system to optimize access time for each specific operation while maintaining adequate charging for reliable read operations.
3Measurement precision
If the bit line is charged to full voltage level, then accurate data retrieval is ensured, but power consumption increases
Solution Approach 1:
The patent modifies the voltage parameter by charging the bit line to a reduced voltage level (sub-VDD) during pre-charge. This parameter change maintains sufficient voltage for accurate data retrieval while significantly reducing the power consumption associated with charging to full voltage levels, especially during low-speed operations.
Solution Approach 2:
The patent applies partial charging action by charging the bit line only to the extent necessary for reliable operation rather than to full voltage. This partial action is sufficient for accurate data retrieval in most cases while avoiding the excessive power consumption that would result from charging to full voltage levels.
Data Source
AI summary
An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.