Cross-Shaped Semiconductor Chip Layout for Stacked Memory Modules
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Solution Overview
Problem
The challenge in developing high-capacity semiconductor modules is the increased total height due to spacers required between stacked semiconductor chips, which can lead to bonding failures when rectangular chips are stacked, as both edges act as overhangs without physical support, increasing the likelihood of bonding wire lift and failure.
Innovation Solution
A semiconductor chip design with a core region and edges that include memory cells and pad portions, allowing for a compact layout that minimizes the area of dummy regions, thereby reducing the length of overhangs when stacked, and ensuring stable bonding by integrating memory cells and pad functions in the edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectangular semiconductor chips are stacked to cross each other to expose pads, then spaces are provided on pads without spacers, but both edges act as overhangs which are not physically supported, causing bonding wires to be more readily lifted and bonding failures
Solution Approach 1:
The patent transitions from a conventional rectangular chip layout to a cross-shaped layout by extending memory cell regions toward the edges. This dimensional reconfiguration allows pads to be positioned at the center of long sides rather than at corners, eliminating the need for spacers while reducing overhang lengths. The cross shape is formed by extending memory cells in the second direction toward the edges, creating a balanced structure where opposite edges are symmetrically positioned.
Solution Approach 2:
The chip is divided into distinct functional regions: a core region containing first memory cells, edge regions containing second memory cells, and pad regions. This segmentation allows the chip to be configured with memory cells extending to the edges, creating a cross-shaped layout that balances the center of gravity and reduces overhangs while maintaining pad accessibility.
2Quantity of substance
If the length of semiconductor chips increases to provide more memory capacity, then more memory cells can be integrated, but the length of overhangs increases causing more bonding failures
Solution Approach 1:
Instead of increasing chip length in the first direction, the patent extends memory cell regions toward the edges in the second direction, creating a cross-shaped layout. This allows the chip to accommodate more memory cells without proportionally increasing the overhang length, as the extended regions are positioned symmetrically to balance the center of gravity and minimize overhang exposure.
3Ease of manufacture
If spacers are disposed between semiconductor chips to provide uniform space, then bonding wires can be connected to pads, but the total height of the semiconductor module increases
Solution Approach 1:
The patent extracts and eliminates the spacer component from the chip stacking structure by redesigning the chip layout. The cross-shaped configuration with memory cells extending to the edges creates inherent spaces for bonding wires without requiring additional spacer elements, thereby maintaining uniform spacing while reducing the overall module height.
Data Source
AI summary
A semiconductor chip includes a core region having a plurality of first memory cells and a first edge adjacent to a first side of the core region. The first edge includes a first region and a second region. The first region includes a plurality of second memory cells, and the second region includes a first pad portion through which at least one of an address signal, a command signal, a clock signal, a data signal and a control signal is inputted or outputted.