8T SRAM Cell Write Assist via Serial NMOS Switches
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Solution Overview
Problem
As the minimum operating voltage of integrated circuits (ICs) decreases, the reliability of SRAM cells is compromised due to reduced read and write operation margins caused by voltage noise, and existing solutions complicate memory design, consume more power, and adversely affect unselected cells.
Innovation Solution
An eight transistor (8T) SRAM cell design featuring a word line, write column select line, and cross-coupled data latch with serially coupled NMOS switch devices, which provides an embedded write-assist mechanism by controlling the write column select line and word line signals to facilitate write operations without affecting unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If VCC_min is decreased to reduce power consumption, then power consumption is reduced, but write operation reliability deteriorates due to reduced margins and voltage noise
Solution Approach 1:
The patent divides the write assist function into two separate NMOS switch devices (first and second NMOS switches) that are serially coupled. This segmentation allows independent control of row and column select signals, enabling precise control of the extra current path without affecting unselected cells, thus maintaining reliability at reduced VCC_min
Solution Approach 2:
The patent introduces an extra current path through the serially coupled NMOS switches before the actual write operation occurs. The write column select line and word line are activated to establish this current path in advance, preparing the cell for reliable write operations at lower voltages by preemptively counteracting voltage noise effects
2Reliability
If peripheral circuitry is added to maintain write reliability, then write operation reliability is maintained, but device complexity increases
Solution Approach 1:
The patent merges the write assist functionality directly into the SRAM cell structure by using the existing bit line, word line, and cross-coupled latch components in combination with the two NMOS switches. This integration eliminates the need for separate peripheral circuitry while maintaining write reliability, thus avoiding increased device complexity
Solution Approach 2:
The serially coupled NMOS switches serve multiple functions: they act as select switches for row and column addressing, provide write assist by creating an extra current path, and prevent interference with unselected cells. This multi-functionality reduces the need for additional dedicated circuitry, simplifying the overall memory design
3Reliability
If write assist is embedded into SRAM cell structure, then write operation reliability is improved, but DC current problems arise that adversely affect unselected cells
Solution Approach 1:
The patent applies local quality control by using the write column select line to independently control the second NMOS switch in each column. This ensures that the extra current path is activated only in the specific column being written to, while unselected columns remain unaffected, thus eliminating the harmful DC current leakage to unselected cells
Solution Approach 2:
The patent implements dynamic control of the extra current path through timed activation of the write column select line and word line. The current path is dynamically enabled only when both select signals are active for the target cell, and disabled otherwise, preventing static DC current flow that would affect unselected cells while maintaining reliability during write operations
Data Source
AI summary
Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.