Absolute Address Branching in Fixed-Width RISC Architectures
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Solution Overview
Problem
In reduced instruction set computing (RISC) architectures, the fixed instruction word width limits the number of address bits available for displacement or absolute address branch instructions, restricting the range of branches that can be supported effectively.
Innovation Solution
The method involves fetching a branch instruction from an instruction stream with a fixed instruction width, acquiring a branch target address value, formatting it as an absolute address sized as a multiple of the instruction width, and loading it into a program counter to redirect execution, allowing for longer branches by using additional instruction words or padding with zeroes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed instruction word width is used in RISC architecture, then instruction execution rate increases and architecture simplicity is maintained, but the number of address bits available for branch instructions is limited, restricting branch range
Solution Approach 1:
The branch target address is segmented into two parts: a first portion contained within the fixed-width branch instruction, and a second portion stored in a separate memory location. This segmentation allows the full address to exceed the instruction word width while maintaining fixed instruction format, thereby extending branch range without sacrificing execution rate.
Solution Approach 2:
The patent extends the address space by moving part of the address information from the horizontal dimension (instruction word bits) to a vertical dimension (separate memory location). This dimensional transition allows the branch target address to utilize more bits than the instruction width by storing additional address bits in memory rather than embedding them all in the instruction.
2Adaptability or versatility
If variable length instruction words are used to support larger address ranges, then branch range capability increases, but instruction set complexity and decoding complexity increase
Solution Approach 1:
The address is divided into segments where the high-order bits are stored in a separate memory location and low-order bits are in the instruction. This segmentation maintains fixed instruction width for simple decoding while enabling extended address range through the additional memory-stored portion.
Solution Approach 2:
A separate memory location acts as an intermediary to store the additional address bits. This intermediary structure enables extended addressing capability without requiring variable-length instructions, thereby avoiding the complexity of variable-length instruction decoding while still achieving the desired address range.
3Adaptability or versatility
If more address bits are allocated in the instruction word, then branch target address range increases, but the number of bits available for other instruction fields decreases
Solution Approach 1:
The patent extracts part of the address information from the instruction word and stores it in a separate memory location. This extraction allows the instruction word to maintain its fixed width with sufficient space for op-code and control fields, while the extracted address portion is retrieved from memory to form the complete branch target address.
Solution Approach 2:
A separate memory location serves as an intermediary structure that holds the additional address bits. This intermediary approach resolves the conflict between instruction width constraints and address range requirements by providing an external storage mechanism for the full address without compromising instruction format flexibility.
Data Source
AI summary
Embodiments relate to a method and computer program product for absolute address branching in a reduced instruction set computing (RISC) architecture. One aspect is a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A branch target address value is acquired from the instruction stream. The branch target address value represents a target address of the branch instruction. The branch target address value is formatted as an absolute address and sized as a multiple of the fixed instruction width. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.