Register Arrangements TRIZ Cases
- RISC Processor Data Path Multiplexer for Specialized Registers
A data path block circuit uses operand multiplexers to interface with specialized register files having distinct read and write port configurations.
- Masking Row Column Positions for Matrix Processing
Masking circuitry skips irrelevant rows and columns in matrix processing, eliminating data remapping overhead and reducing latency.
- Vector Load Immediate Decimal Instruction for Register Population
A Vector Load Immediate Decimal instruction generates signed packed decimal values directly within a register using sign control and shift operations.
- Dynamic Instruction Merging for Wide Data Path Execution
A predecoder merges legacy instructions into single executable units for wide datapath processing.
- Microcontroller Banking Instructions for Contiguous Memory Access
Non-memory mapped bank select register allows contiguous access to larger memory blocks without special function registers interrupting data areas.
- Vector Instruction Format for Packed Byte Multiply-Accumulate
A vector friendly instruction format executes simultaneous multiplication, summation, and accumulation of packed signed bytes within a single operation cycle.
- Absolute Address Branching in Fixed-Width RISC Architectures
Segmenting the branch target address across the fixed-width instruction and separate memory extends the address range without increasing decoding complexity.
- Dynamic Register Virtualization for ROP Attack Defense
Processor randomizes register mappings at subroutine calls to disrupt return-oriented programming attacks without adding hardware complexity.
- Vector Packed Multiply Rounding and Saturation Control
New instructions merge multiplication, rounding, and saturation into single operations to resolve precision versus versatility trade-offs.