Vector Instruction Format for Packed Byte Multiply-Accumulate
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Solution Overview
Problem
Existing single instruction multiple data (SIMD) microarchitectures require sequential execution of instructions for multiply-accumulate operations, which can be inefficient for digital signal processing tasks involving packed bytes.
Innovation Solution
A vector friendly instruction format that supports packed byte operations, allowing for simultaneous multiplication, summation, and accumulation of packed bytes within a single instruction, utilizing a generic vector friendly instruction format with specific fields for operation control, memory access, and data manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential instruction execution is used for multiply-accumulate operations, then existing SIMD microarchitectures can be maintained with simple instruction formats, but execution efficiency and throughput are reduced
Solution Approach 1:
The patent combines multiple operations (multiplication, addition, and accumulation) into a single unified instruction. The execution unit performs all three operations simultaneously on packed byte data, eliminating the need for sequential instruction execution and thereby improving execution efficiency without requiring complex multi-instruction sequences
Solution Approach 2:
The instruction format is designed to be universal and support multiple data types and operations through a single instruction structure. The execution unit can handle packed bytes, words, and doublewords using the same instruction template, reducing the need for multiple specialized instructions while maintaining simplicity
2Productivity
If multiple separate instructions are used for multiply, sum, and accumulate operations, then instruction precision and control are maintained, but the number of instructions increases and throughput decreases
Solution Approach 1:
The patent merges multiply, sum, and accumulate operations into a single atomic instruction that executes in one cycle. This unified approach increases throughput by processing all operations simultaneously while maintaining precise control through a single instruction stream without requiring complex sequencing of multiple instructions
Solution Approach 2:
The instruction is designed with pre-configured operation codes and data type specifications that define the entire multiply-accumulate sequence in advance. The execution unit retrieves and executes the complete operation sequence from a single instruction, eliminating the need for multiple control steps and improving throughput
Data Source
AI summary
A processor having a decoder to decode an instruction to generate a decoded instruction; a first source register to store a first plurality of packed signed bytes; a second source register to store a second plurality of packed signed bytes; execution circuitry to execute the decoded instruction, the execution circuitry including: multiplier circuitry to multiply each packed signed byte from the first source register with a corresponding packed signed byte from the second source register to generate temporary products, adder circuitry to add a plurality of sets of the temporary products to generate a plurality of temporary sums; negation and extension circuitry to negate and extend each of the temporary sums to doublewords sums; and accumulation circuitry to add each of the doublewords sums to a doubleword from a third source register to generate final doubleword results; and a packed data destination register to store the final doubleword results.