RISC Processor Data Path Multiplexer for Specialized Registers

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Solution Overview

Problem

RISC processors require efficient data path circuits that interact with specialized registers, as existing designs consume significant die area and power due to the need for multiple types of registers with varying read and write ports.

Innovation Solution

The implementation of a data path block circuit with multiplexers and logic circuits that selectively use registers with different port configurations, allowing for efficient interaction with specialized register files having unique read and write port quantities, thereby reducing die area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If each register is implemented with all features needed for each type of calculation variable, then the data path can interact with each register file identically, but the die area and power consumption increase significantly

Engineering Contradiction:
Improveregister versatilityVSAvoiddie area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent divides the register system into specialized register files (integer registers, floating-point registers, vector registers) with different port configurations. Each register file is segmented to have specific read/write port quantities matched to its intended use, rather than all registers having identical full-featured ports.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different register files are given different local qualities in terms of port configurations. Integer registers have more read ports for arithmetic operations, floating-point registers have different configurations for scientific calculations, and vector registers have specialized ports for parallel data processing. This local differentiation reduces overall die area while maintaining functionality.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If each register is implemented with all features needed for each type of calculation variable, then the data path can interact with each register file identically, but the power consumption increases significantly

Engineering Contradiction:
Improveregister versatilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The register system is segmented into specialized files that only activate the port configurations needed for their specific purposes. This segmentation prevents unnecessary power consumption in ports that are not used by particular register types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each register file has locally optimized power characteristics based on its specific function. Registers used for integer arithmetic have power-optimized read port configurations, while floating-point registers have different power characteristics suited to their operations, reducing overall power consumption compared to a uniform high-power design.

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If specialized register files with different port configurations are used, then die area and power consumption are reduced, but the data path must selectively access different register files

Engineering Contradiction:
Improvedie areaVSAvoiddata path complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent introduces intermediary multiplexer circuits that act as mediators between the data path and the specialized register files. These multiplexers selectively route data to and from the appropriate register file based on the operation type, managing the complexity of accessing multiple specialized registers through a unified interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11243905B1RISC processor having specialized data path for specialized registers
Publication Date: 2022.02.08 SHENZHEN GOODIX TECH CO LTD
  • US11243905B1 patent drawing
  • US11243905B1 patent drawing
  • US11243905B1 patent drawing

AI summary

A data path block circuit is disclosed. The data path block circuit includes a data path circuit having logic circuits, each configured to perform a data path operation to generate a result based on first and second operands. The data path block circuit also includes a first operand multiplexer, having inputs, each connected to one of a first register file, including a quantity of read and write ports, and a second register file, including a different quantity of read and write ports. The data path block circuit also includes a second operand multiplexer, having inputs, each connected to one of the first register file and the second register file. At least one of the first and second operand multiplexers includes a data input connected to the first register file. At least one of the first and second operand multiplexers includes a data input connected to the second register file.