Microcontroller Banking Instructions for Contiguous Memory Access
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Solution Overview
Problem
Smaller microcontroller architectures, such as 8-bit processors, face challenges in addressing large linear memory spaces due to limited instruction length, which restricts direct access to memory and requires memory banking, but this approach often results in non-contiguous data memory with special function registers interrupting memory blocks, limiting access to larger memory areas.
Innovation Solution
A non-memory mapped bank select register (BSR) is introduced, allowing direct and indirect addressing across multiple memory banks without special function registers, enabling contiguous addressing and access to larger memory blocks through a specialized banking instruction, 'Move Literal to BSR Register (MOVLB)', which selects the active memory bank independently of special function registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory banking is used to access large memory spaces in 8-bit microcontrollers, then memory accessibility is improved, but data memory contiguity deteriorates due to special function registers interrupting memory blocks
Solution Approach 1:
The data memory is divided into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3), each containing a subset of special function registers. This segmentation allows the memory to be accessed in contiguous 256-byte blocks while distributing SFRs across different banks, thereby resolving the contradiction between memory accessibility and data memory contiguity.
Solution Approach 2:
The patent introduces a bank select register (BSR) that adds a new dimension to memory addressing. By combining the BSR with the data memory address, the system can access any 256-byte bank contiguously, effectively transforming the addressing space from one-dimensional to two-dimensional (bank selection + offset within bank), thus maintaining contiguity while enabling access to larger memory spaces.
2Speed
If special function registers are mapped into data memory for critical access, then register accessibility is improved, but memory contiguity deteriorates
Solution Approach 1:
Special function registers are segmented across multiple memory banks rather than being集中 in a single bank. Each bank contains a subset of SFRs, allowing critical registers to be accessed quickly from their respective banks while maintaining contiguous memory blocks within each bank.
Solution Approach 2:
The bank select register (BSR) acts as an intermediary that enables fast access to specific banks containing critical special function registers. By selecting the appropriate bank before accessing an SFR, the system maintains both fast accessibility and memory contiguity within each bank.
3Quantity of substance
If multiple banks are used to expand memory capacity, then memory capacity is improved, but addressing complexity increases
Solution Approach 1:
The bank select register (BSR) and data memory address are merged into a unified addressing mechanism. The BSR provides the upper bits of the address while the data memory address provides the lower bits, creating a seamless 16-bit addressing space that simplifies access to expanded memory capacity without increasing addressing complexity.
Solution Approach 2:
The BSR serves multiple functions: it selects the active memory bank, enables contiguous addressing across banks, and works seamlessly with both direct and indirect addressing modes. This multi-functionality expands memory capacity while maintaining simple, unified addressing syntax.
Data Source
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AI summary
An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.