Accelerator Circuit for Off-Chip Memory to Internal Transfer
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Solution Overview
Problem
High-performance microcontroller units (MCUs) without internal Flash memory rely on off-chip memory for storing application content, leading to slower code execution and longer boot times due to the slower speed of external Flash technologies compared to internal Flash.
Innovation Solution
An accelerator circuit, including a direct memory access (DMA) circuit and a decoder circuit, is used to intelligently move content from off-chip memory to internal memory, allowing the CPU to execute applications from internal memory while the content mirroring operation is in progress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If off-chip memory is used to store application content, then device complexity is reduced, but code execution speed deteriorates
Solution Approach 1:
The accelerator circuit performs preliminary copying of content from off-chip memory to internal memory before the processor needs to execute it. This preliminary action ensures that when the processor requests content, it is already available in the faster internal memory, resolving the speed penalty of using off-chip storage.
Solution Approach 2:
The accelerator circuit acts as an intermediary between the off-chip memory and the processor. It manages the content copying operations and coordinates access to both memory types, enabling the processor to benefit from fast internal memory while utilizing the storage capacity of off-chip memory.
2Speed
If content is copied from off-chip memory to internal memory, then code execution speed is improved, but boot time deteriorates
Solution Approach 1:
The accelerator circuit initiates content copying from off-chip memory to internal memory in advance, before the processor needs to execute the content. This overlapping of operations allows the processor to start executing code while the copying is still in progress, dramatically reducing boot time.
Solution Approach 2:
The system maintains continuous useful action by having the accelerator circuit copy content in the background while the processor executes other instructions. This continuous operation eliminates the sequential bottleneck where copying would have to wait for processor readiness, thereby reducing overall boot time.
3Productivity
If content mirroring is performed during CPU execution, then productivity is improved, but device complexity increases
Solution Approach 1:
The accelerator circuit serves as an intermediary that handles the content copying operations independently of the processor. This separation allows the processor to focus on execution while the accelerator manages the complexity of coordinating memory access, copying operations, and cache management.
Solution Approach 2:
The accelerator circuit autonomously manages the content copying process without requiring continuous processor intervention. It self-coordinates the copying operations, manages cache coherence, and handles memory access patterns, thereby improving productivity while containing the added complexity within the accelerator itself.
Data Source
AI summary
An example accelerator circuit includes a direct memory access (DMA) circuit configured to copy contents of an off-chip memory to an internal memory of a device. In some examples, the off-chip memory is external to the device. The example accelerator circuit also includes a decoder circuit configured to determine a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory. In some examples, the decoder circuit is also configured to direct the transaction to one of the off-chip memory or the internal memory based on whether a DMA copy of the region of the off-chip memory to the internal memory has completed.