Electric Digital Data Processing TRIZ Cases
- DMA Data Migration with Dual-Write Consistency
A data processing system migrates direct memory access pages by fetching reads from the source and storing writes in both locations.
- Interface Extension Device for USB 2.0 and 3.0 Compatibility
A dual-host interface extension device supports both USB 2.0 and USB 3.0 standards through segmented circuitry.
- SoC Transaction Ordering via Pointer Values
Ordering circuitry generates pointer values to track transaction IDs and ensure correct data packet transmission sequence.
- Memory Controller Interrupt Generation for Multi-Processor Systems
Hardware-based interrupt generation eliminates software context switching delays in multi-processor systems.
- Bus Control Circuit Arbitration for Semiconductor Data Transfer
A bus control circuit arbitrates data transfer between multiple bus masters and slaves using priority-based access.
- Memory Controller Write Queue Logic for Storage Class Memory
Write queue logic buffers address and time values to ensure deterministic write operations, resolving latency trade-offs in non-volatile memory technologies.
- SAS Discovery Traffic Reduction via BCR Count Comparison
A SAS discovery node compares broadcast change received counts to identify affected expanders.
- Real-Time Controller for Shared Data Bus Rate Management
A controller regulates maximum data rates on a shared bus by dividing data into blocks and allocating transmission intervals.
- PCIe SSD Redundant Path Architecture for High Availability
Dual port logic segments a single PCIe interface into independent paths, enabling failover between controllers without serial protocol bottlenecks.
- Location-Aware Peripheral Device Self-Configuration
A peripheral device selects its operational personality based on its physical attachment location within a computing system.
- Elastic FIFO Multi-Source Selector for Low-Latency Data Pipelines
An elastic FIFO structure manages data flow through a multi-source selector to enable efficient insertion.
- Advanced Switching Unit for PCIe Domain Separation
An advanced switching unit converts addresses and Requester IDs between system hosts and local devices.
- Application-Specific I/O Queues for SSD Access Control
Segmented I/O submission queues prevent request collisions between applications sharing a single semiconductor storage device.
- Accelerator Circuit for Off-Chip Memory to Internal Transfer
An accelerator circuit moves off-chip memory contents to internal storage using a DMA and decoder mechanism.
- Northbridge Protocol Translation for HyperTransport to PCI Express
A Northbridge translates memory write requests between HyperTransport and PCI Express protocols.
- IOMMU Shared Memory Accelerator Invocation
An IOMMU translates virtual addresses for accelerator memory access requests, reducing processing time and power consumption by eliminating CPU intervention.
- Memory Controller Register Management for Shared Memory Systems
A memory controller manages multiple registers to allocate and deallocate shared memory spaces efficiently.
- eUSB Repeater Detector Circuit for Low Power Start Signaling
A detection circuit in an eUSB repeater generates wake signals upon detecting start signaling on the bus.
- SAS Expander Address Duplication Detection
Root expander detects duplicate SAS addresses during topology discovery using Vendor Unique SMP commands to prevent incomplete system discovery.
- PCIe Switching Network Host Sharing via Managing Unit
A managing unit establishes routing paths between switch terminal devices to enable multiple hosts to share a PCIe switching network.
- USB Hub Dynamic Role Switching Protocol
A configurable USB hub reconfigures downstream ports to upstream roles, enabling connected devices to operate as hosts.
- Dual Bus Matrix Architecture for Microcontroller Bandwidth Routing
Segmenting the system bus into dedicated high and low bandwidth matrices resolves routability bottlenecks caused by heterogeneous peripheral requirements.
- PCIe Transmit Descriptor Bandwidth Optimization
Embedding packet data into transmit descriptors reduces transaction level packets, resolving bandwidth inefficiency for varying Ethernet sizes.
- Interconnect for Shared Control Electronics in Mass Data Storage
An interconnect transmits analog read/write signals between shared control electronics and individually selectable storage drives.
- Bonding Circuit for Memory Controller Width Merging
Hard logic bonding circuit coordinates separate memory controllers to function as a unified N+M bit wide unit, reducing die area and design costs.
- Multi-Interface Bridge for Network Packet Processor Counter Aggregation
A multi-interface bridge aggregates counter values from multiple physical interfaces into a universal address map within the packet processor.
- Resource Controller Priority Accounting for SoC Bandwidth
A resource controller uses an up-down counter to block high priority requests when low priority service drops below a threshold.
- Persistent USB Device Enumeration via Pre-stored Descriptors
Pre-storing hashed USB descriptors in the host controller reduces initialization time by bypassing full enumeration sequences for persistent automotive devices.
- BMC I2C Multiplexor for Test Access and Fault Injection
A baseboard management controller multiplexor routes multiple device I2C buses to a single external interface via selectable buffer circuits.
- Interconnect Region Ordering for Latency Reduction
Partitioning logical server regions into orderable zones lets clients push ordering responsibility to servers, reducing latency on un-ordered interconnects.
- Memory Controller Parallel Serial Bus Pin Reduction
A memory controller manages parallel and serial command buses to reduce signal pin count.
- AXI-to-Memory Protocol Bridge Latency Reduction
An AXI-to-memory IP protocol bridge serializes transactions via queuing buffers to enable parallel processing.
- I/O Control Circuit for OCP Bifurcation Timing
Local I/O control circuit generates bifurcation signals during auxiliary power transitions, eliminating BMC dependency and reducing system boot time.
- Modular NVMe Storage Appliance with Autonomous Network Cards
Segmented modular architecture expands supported NVMe device count beyond 8-bit address limits while removing host processor integration burden.
- Optical Transceiver Configuration Update via Shared Bus
Shared bus updates transceiver configuration without extra switching circuits, preventing communication loss during firmware changes.
- Embedded Control Circuit Dual Bus Peripheral Access
Segmented bus paths resolve conflicts between host and embedded processor access, boosting bandwidth.
- UAI Translator for MIL-STD-1760 Legacy Avionics Integration
A UAI translator converts messages between legacy MIL-STD-1760 and Universal Armament Interface protocols.
- USB Host Divides Data Stream for Multi-Channel Bandwidth
A USB host divides a data stream into sub-streams transmitted via multiple channels to increase bandwidth.
- Protocol-Aware Bridge Circuit for Low Latency IC Communication
A protocol-aware bridge circuit packetizes parallel data into serial streams to enable high-speed inter-IC communication.
- Memory Control Chip Write Protection Detection
Control chip detects memory device protocol and write protection switch status to initialize the correct transmission interface.
- Motherboard Demultiplexer for PCIe Signal Routing
A motherboard demultiplexer routes PCIe signal pairs to buses or riser slots based on hardware presence.
- Generic Interface Microcontroller for Vehicle Control Units
A microcontroller with generic interface modules emulates multiple serial protocols to enable flexible data processing.
- Reconfigurable Fabric DMA with Hierarchical Circular Buffers
Hierarchical circular buffers control switching elements in a reconfigurable fabric to boost data transfer efficiency while managing device complexity.
- Pattern-Based Service Bus Architecture for Scalable SOA
A pattern-based service bus standardizes interactions between distributed participants through a unified intermediary.
- ULPI PHY USB 2.0 Link Power Management PID Transmission
A ULPI transceiver configures operation modes to transmit reserved PID tokens over the bus.
- PCIe Precision Timing Measurement Uncertainty Reduction
Synchronizing PTM messages with SSC modulation cycles reduces delay uncertainty without bandwidth overhead.
- Chipset Lane Configuration Module for Dynamic Bandwidth Allocation
A configuration module dynamically assigns lanes to access ports in a chipset.
- Multi-Master SPI Bus Arbitration Interface
Arbitration interface resolves signal collisions by granting exclusive bus control to one master device at a time.
- PCIe Shunt Circuit for Direct Accelerator Linking
Shunt circuit routes PCIe data via internal bus, bypassing CPU to resolve link congestion.
- USB Controller Connection Detection via Voltage Level Monitoring
A USB controller monitors voltage levels on power and data contacts to determine device connection status through a switch module.