I/O Control Circuit for OCP Bifurcation Timing
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Solution Overview
Problem
The existing Open Compute Project (OCP) 3.0 specifications for bifurcation control in computing systems face timing issues due to the reliance on baseboard management controllers (BMC) or platform controller hubs (PCH) for sending bifurcation control signals, leading to delays and inefficiencies in power-on sequences, particularly during the auxiliary power mode transition.
Innovation Solution
An input/output control circuit is introduced that provides a bifurcation control signal to OCP devices during the auxiliary power phase transition period, independent of BMC or PCH, using a non-volatile memory to store settings and activate the bifurcation function before the main power mode is reached, thus enabling bifurcation control in a single power cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BMC or PCH is used to send bifurcation control signals according to OCP 3.0 Specification, then bifurcation control functionality is achieved, but timing requirements cannot be met during auxiliary power mode transition
Solution Approach 1:
The patent extracts the bifurcation control signal generation function from the BMC/PCH and implements it directly in the OCP device. The device includes a control circuit that generates the bifurcation control signal locally during the auxiliary power mode transition, eliminating the dependency on external controllers and their firmware boot delays.
Solution Approach 2:
The patent implements preliminary action by enabling the bifurcation control signal generation to occur during the auxiliary power mode transition, before the main power mode is activated. This ensures the bifurcation setting is completed in advance, meeting the OCP specification requirement that bifurcation must be established before main power operation.
2Reliability
If CPLD is used to delay enable power signal until BMC firmware boot completes, then bifurcation control timing is resolved, but system boot time increases significantly
Solution Approach 1:
The patent applies self-service by enabling the OCP device to generate its own bifurcation control signal independently, without requiring the BMC firmware to boot first. The device uses its own power sequence and internal control logic to establish bifurcation, eliminating the need to wait for external controller initialization.
Solution Approach 2:
The bifurcation control signal is generated during the auxiliary power mode transition, which occurs before main power mode activation. This preliminary action ensures bifurcation is established in advance, eliminating the need to delay the enable power signal until BMC firmware completes its boot process.
3Reliability
If additional power cycle is required for PCH GPIO pins to be ready, then bifurcation control can be implemented, but power-on sequence becomes more complex and time-consuming
Solution Approach 1:
The patent removes the dependency on PCH GPIO pins by implementing the bifurcation control signal generation within the OCP device itself. This extraction eliminates the need for additional power cycles to wait for PCH GPIO readiness, simplifying the power-on sequence to a single cycle.
Solution Approach 2:
The device prepares and generates the bifurcation control signal during the auxiliary power mode transition, ensuring readiness before main power mode activation. This preliminary preparation eliminates the need for multiple power cycles and complex sequencing.
Data Source
AI summary
A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.