Northbridge Protocol Translation for HyperTransport to PCI Express
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems, the difference in protocols between HyperTransport and PCI Express causes issues with passing memory write requests, particularly non-posted commands, through the Northbridge to the Southbridge, leading to deadlocks due to the LPC interface's inability to handle retries and recognize non-posted memory write requests.
Innovation Solution
A method and apparatus that translate memory write requests from HyperTransport to PCI Express by inserting a predefined code into the PCI Express formatted requests, allowing the Southbridge to recognize and acknowledge non-posted writes, thereby preventing deadlocks by converting all transactions to a format recognizable by the PCI Express protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the Northbridge translates HyperTransport protocol to PCI Express protocol, then compatibility between CPU and Southbridge is improved, but non-posted memory write requests cannot be properly transmitted causing deadlocks
Solution Approach 1:
The Northbridge acts as an intermediary device between the HyperTransport interface and PCI Express interface. It receives memory write requests from the CPU via HyperTransport, translates them to PCI Express protocol, and transmits them to the Southbridge. This mediator approach resolves the protocol incompatibility while maintaining transaction reliability through proper translation of posted and non-posted write semantics.
Solution Approach 2:
The translation process changes the protocol parameters from HyperTransport to PCI Express. Specifically, the Northbridge transforms the message format, command types, and transmission semantics to match PCI Express requirements. This parameter transformation enables compatibility between the two protocols while preserving the essential functionality of memory write requests.
2Productivity
If the LPC interface master holds control of the interface, then direct memory access reads can be performed, but posted memory write requests from the CPU cannot be completed causing system deadlock
Solution Approach 1:
The translation mechanism implements feedback by monitoring the state of memory write requests and the LPC interface master status. When a non-posted write request is translated to PCI Express, the system can track its completion status and provide appropriate feedback to the CPU. This feedback mechanism prevents deadlocks by ensuring that write requests are properly acknowledged even when the LPC interface is busy.
Solution Approach 2:
The system dynamically adjusts its behavior based on the state of the LPC interface. When the interface master is performing DMA reads, the translation logic adapts by queuing or retransmitting write requests at appropriate times. This dynamic response allows the system to maintain both DMA read performance and write request completion reliability.
Data Source
AI summary
Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types. The predefined code in the received memory write request is then used to determine the type of memory write request (posted or non-posted).


