PCIe Transmit Descriptor Bandwidth Optimization

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Solution Overview

Problem

The PCIe interface's bandwidth is inefficiently utilized when handling Ethernet packets of varying sizes, as existing methods require multiple transaction layer packets (TLPs) even for small data transactions, leading to reduced interface utilization, especially in cases where the packet size is slightly larger than the TLP size.

Innovation Solution

The proposal involves augmenting transmit descriptors to include a portion or entirety of the packet data, allowing for more efficient utilization of the PCIe interface by reducing the number of TLPs needed to transfer packet data from host memory to NIC memory, with optional padding to match the TLP size, thereby optimizing bandwidth utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple TLP packets are used to transfer packet data from host memory to NIC memory, then data transfer is ensured, but PCIe interface bandwidth utilization is dramatically reduced

Engineering Contradiction:
ImprovePCIe interface bandwidth utilizationVSAvoidnumber of TLP transactions
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent combines the transmit descriptor and packet data into a single TLP packet for transfer over the PCIe interface. Instead of sending separate TLP packets for descriptors and data, the invention merges them into one unified transfer unit, thereby reducing the total number of TLP transactions and improving bandwidth utilization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary action by padding the transmit descriptor with packet data before the PCIe transfer occurs. The host system prepares the combined descriptor-data structure in advance, ensuring that when the TLP transfer happens, the data is already organized and ready, reducing the need for additional transactions.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If fixed-size TLP packets are used for PCIe communication, then protocol simplicity is maintained, but bandwidth efficiency is reduced when Ethernet packet size exceeds TLP size

Engineering Contradiction:
Improvebandwidth efficiencyVSAvoidpacket structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the combined descriptor and packet data into fixed-size TLP packets while maintaining the logical connection between them. The transmit descriptor is divided into multiple TLP packets, with each packet containing a portion of the descriptor and associated packet data, allowing fixed-size transfers while preserving bandwidth efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of packet structure by introducing a hybrid format where the transmit descriptor is augmented with packet data. This creates a new data structure that optimizes for both fixed-size TLP requirements and bandwidth efficiency, transforming the traditional separate descriptor-data structure into an integrated format.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240028550A1LAN pcie bandwidth optimization
Publication Date: 2024.01.25 INTEL CORP
  • US20240028550A1 patent drawing
  • US20240028550A1 patent drawing
  • US20240028550A1 patent drawing

AI summary

Methods and apparatus for LAN PCIe bandwidth optimization. Packets to be sent outbound onto a network are generated and buffered in memory on a host computing device. Transmit (Tx) descriptors associated with respective packets are generated comprising descriptor data and at least a portion of the packet data for the packet, where the descriptor data are configured to be processed by a network apparatus coupled to the network, such as a network interface controller (NIC) or network adapter. Tx descriptors are transferred from host memory to the network apparatus over a Peripheral Component Internet Express (PCIe) interconnect using a single respective transaction level packet (TLP) per Tx descriptor. This increases bandwidth utilization for the PCIe interconnect by reducing the number of TLPs that are used to transfer Tx descriptors and packet data to the network apparatus. The novel Tx descriptors may be used for LAN and Wireless LANs.