Memory Controller Register Management for Shared Memory Systems
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Solution Overview
Problem
Existing computing systems face challenges in managing data dependencies and synchronizations in shared memory mechanisms, particularly when multiple computing engines with different throughput perform concurrent read and write operations.
Innovation Solution
A computing system architecture that utilizes a memory device with a memory controller managing multiple registers to allocate and deallocate memory spaces efficiently, employing a managing table to record essential parameters and indicators for each register, thereby resolving data dependency issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared memory mechanism is utilized to simplify memory management, then memory management complexity is reduced, but data dependency issues arise when multiple computing engines perform concurrent read and write operations
Solution Approach 1:
The patent divides the shared memory into multiple memory spaces, each associated with a specific computing engine. This segmentation allows independent memory regions for each engine while maintaining overall shared memory architecture, thereby simplifying memory management while preventing data dependency conflicts through dedicated regions.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between computing engines and memory storage. The memory controller manages memory spaces, handles concurrent access requests, and coordinates read/write operations between multiple computing engines, thereby resolving data dependency issues without requiring complex synchronization mechanisms.
2Reliability
If dedicated memory units are used for each computing engine, then data access independence is improved, but complex management and synchronization are required
Solution Approach 1:
The patent implements a unified memory architecture where a single memory storage is shared by multiple computing engines through a common memory controller. This universal memory system provides multi-functionality by serving multiple engines simultaneously while maintaining organized memory spaces, thereby reducing overall system complexity compared to separate dedicated memory units.
3Productivity
If concurrent read and write operations are executed in shared memory, then computing throughput is improved, but data dependency conflicts occur between computing engines with different throughput
Solution Approach 1:
The patent implements dynamic memory space management where the memory controller can allocate, reallocate, and manage memory spaces based on the operational needs of different computing engines. This dynamic approach allows the system to adapt memory distribution to current workload patterns, enabling high throughput while maintaining data consistency through flexible memory management.
Data Source
AI summary
A computing system, includes a memory device, which further includes a memory storage and a memory controller. The memory controller is used to utilize a plurality of registers to manage a plurality of memory spaces in the memory storage. Several of computing engines, are used to execute a plurality of computations, read a plurality of consumed data from the memory storage for processing, and write the processed data as produced data to the memory storage. The memory controller utilizes a managing table to record an identifier, a base address, a bound address, a delete size, a head pointer, a tail pointer, and two indicators of each of the registers.