Dual Bus Matrix Architecture for Microcontroller Bandwidth Routing
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Solution Overview
Problem
The increasing number of peripherals with heterogeneous bandwidth requirements and different clock frequencies on a system bus creates routability issues, leading to performance reduction, as existing single bus matrix architectures struggle to match these diverse requirements effectively.
Innovation Solution
A dual bus matrix architecture is employed, with a first matrix for high-bandwidth peripherals and a second matrix for limited-bandwidth peripherals, connected through a shared multiport controller that schedules accesses to optimize shared memory usage, allowing both types of peripherals to access memory directly without the need for additional logic or redesign.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bus matrix is used to connect all peripherals, then device complexity is reduced, but routability and performance deteriorate due to heterogeneous bandwidth requirements
Solution Approach 1:
The single bus matrix is segmented into two separate bus matrices: a first bus matrix for high-bandwidth peripherals and a second bus matrix for limited-bandwidth peripherals. This segmentation allows each matrix to be optimized for its specific bandwidth requirements, improving routability without significantly increasing overall system complexity.
Solution Approach 2:
Different bus matrices are provided with different qualities characteristics - the first bus matrix is designed for high bandwidth operations while the second is designed for limited bandwidth operations. This local quality differentiation allows each peripheral to access the bus matrix with appropriate bandwidth characteristics, resolving the routability issue.
2Adaptability or versatility
If wrapper logic is added to match heterogeneous peripheral requirements, then adaptability improves, but performance deteriorates
Solution Approach 1:
Instead of adding wrapper logic to a single bus matrix, the system segments peripherals into two groups and connects them to specialized bus matrices. High-bandwidth peripherals connect to the first matrix and limited-bandwidth peripherals connect to the second matrix, eliminating the need for wrapper logic while maintaining adaptability and preserving performance.
3Ease of manufacture
If all peripherals are connected to the same bus matrix, then ease of manufacture is improved, but bandwidth matching capability deteriorates
Solution Approach 1:
The system applies local quality by providing different bus matrix characteristics to different peripheral groups. The first bus matrix offers high bandwidth for peripherals requiring it, while the second bus matrix provides limited bandwidth for peripherals that don't require high bandwidth. This approach maintains ease of manufacture through standardized interfaces while achieving excellent bandwidth matching capability.
Data Source
AI summary
A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.