Motherboard Demultiplexer for PCIe Signal Routing
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Solution Overview
Problem
Motherboards face challenges in accommodating varying chassis sizes, as they can support fewer peripheral card slots in smaller chassis due to space limitations, necessitating separate designs for different sizes, which increases design complexity and costs.
Innovation Solution
The implementation of a demultiplexer that selectively routes signal pairs to PCIe buses and riser slots based on the presence or absence of a riser card, allowing the same motherboard to support more or fewer peripheral card slots depending on the chassis size, thereby enabling flexibility without requiring separate motherboard designs for different sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the motherboard is designed to support more peripheral card slots, then the adaptability to different chassis sizes is improved, but the device complexity increases due to routing challenges
Solution Approach 1:
The signal pairs are segmented and routed to different destinations (PCIe buses or riser slots) based on the presence or absence of a riser card. The motherboard includes multiple PCIe buses (first PCIe bus, second PCIe bus) and riser slots that can be selectively activated, dividing the peripheral card slot functionality into separate routable paths rather than having all slots permanently connected to all signal pairs.
Solution Approach 2:
The motherboard configuration is made dynamic through the demultiplexer functionality that selectively routes signal pairs based on the riser card presence. When a riser card is detected, signal pairs are routed to riser slots; when absent, the same signal pairs are routed to PCIe buses. This dynamic routing allows the same motherboard to adapt its configuration to different chassis sizes without requiring separate designs.
2Manufacturing precision
If separate motherboard designs are created for different chassis sizes, then the manufacturing precision for specific chassis is improved, but the device complexity and design costs increase
Solution Approach 1:
The motherboard is designed as a universal platform that can function in both larger and smaller chassis configurations. The same motherboard includes PCIe buses and riser slots that can be selectively activated based on the chassis size and riser card presence. This multi-functional design eliminates the need for separate motherboard designs for different chassis sizes while maintaining manufacturing precision through consistent routing structures that adapt to the specific configuration.
Solution Approach 2:
The riser card acts as an intermediary that determines the routing configuration. When present, it mediates the connection between signal pairs and riser slots; when absent, the routing is mediated to connect signal pairs to PCIe buses instead. This intermediary mechanism allows a single motherboard design to accurately configure itself for different chassis sizes without requiring multiple specialized designs.
3Device complexity
If the motherboard supports fewer peripheral card slots, then the device complexity is reduced, but the adaptability to larger chassis sizes deteriorates
Solution Approach 1:
The motherboard dynamically adjusts its operational configuration based on the riser card presence and chassis size. The same physical motherboard can operate with fewer active peripheral card slots in smaller chassis (reducing effective complexity) or with more active slots in larger chassis (increasing adaptability). The routing logic dynamically enables or disables specific PCIe buses and riser slots to match the actual hardware configuration, allowing the motherboard to support varying numbers of peripheral card slots without requiring multiple designs.
Data Source
AI summary
Example implementations relate to route demultiplexed signal pairs. In some examples, a motherboard of a computing device can include a chipset, a first Peripheral Component Interconnect Express (PCIe) bus, a second PCIe bus, a riser slot, and a demultiplexer connected to the chipset to selectively route particular signal pairs from the chipset to at least one of the first PCIe bus, the second PCIe bus, and the riser slot based on whether a riser card is connected to the riser slot.