Protocol-Aware Bridge Circuit for Low Latency IC Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional inter-IC communication in multi-IC systems, such as emulation systems, faces bottlenecks due to limitations in Select I/O speed and scalability, leading to reduced emulation clock frequencies and increased partitioning and implementation times as circuit design sizes grow.
Innovation Solution
The implementation of bridge circuits with multi-gigabit transceivers that establish asynchronous serial communication links between ICs, allowing for high-speed data transmission and bypassing the limitations of Select I/O by packetizing and depacketizing data across IC boundaries, enabling efficient communication and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Select I/O is used for inter-IC communication, then cycle accurate data transmission is achieved, but data throughput is limited and latency increases
Solution Approach 1:
A bridge circuit is introduced as an intermediary component between ICs to enable high-speed serial communication. The bridge circuit includes transceivers that convert parallel Select I/O signals to serial data for transmission over asynchronous serial links, and vice versa, thereby mediating between the reliability requirements of cycle-accurate emulation and the productivity requirements of high-speed data transfer
Solution Approach 2:
The communication interface parameters are changed from synchronous Select I/O to asynchronous serial communication. The bridge circuit transforms the data format and transmission parameters, allowing multi-gigabit per second serial transmission that bypasses the throughput limitations of traditional Select I/O while maintaining protocol awareness for reliable data transfer
2Quantity of substance
If multiplexing ratio increases to accommodate more nets, then more data can be transmitted, but emulation clock frequency decreases
Solution Approach 1:
The patent replaces the mechanical multiplexing system with an asynchronous serial communication system. Instead of time-division multiplexing Select I/O signals, the bridge circuit uses packetized data transmission over serial links, eliminating the direct trade-off between the number of nets and clock frequency while maintaining the ability to transmit multiple data streams simultaneously
3Productivity
If Select I/O is used for communication, then inter-IC data transmission is achieved, but implementation time increases
Solution Approach 1:
The bridge circuit is pre-configured with protocol awareness and packetization capabilities during the implementation phase. This preliminary setup enables automatic handling of data format conversion and transmission protocols, reducing the time required for partitioning and implementation by eliminating manual configuration requirements
Data Source
AI summary
A system includes a bridge circuit configured for low latency communication among integrated circuits (ICs). The bridge circuit includes a plurality of transceiver circuits. Each transceiver circuit is coupled to a corresponding parallel channel in the IC. Each transceiver circuit is configured to send and receive data over the corresponding parallel channel. Each transceiver circuit includes a transmit channel configured to packetized data received from the corresponding parallel channel for transmission over a serial link to a second IC. Each transceiver circuit includes a receive channel configured to depacketize data received from the serial link from the second IC. The serial link is asynchronous to each of parallel channel coupled to the first bridge circuit.