PCIe SSD Redundant Path Architecture for High Availability

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Solution Overview

Problem

High availability storage systems face challenges in maintaining data accessibility when a single point of failure occurs, as they typically rely on serial storage protocols and hard disk drives, which are less efficient compared to Solid State Drives (SSDs) in handling redundant paths and failover scenarios.

Innovation Solution

The implementation of a redundant Peripheral Component Interconnect Express (PCIe) path to a PCIe Solid State Drive (SSD) using dual port/single port logic and PCIe Non Transparent Bridge (NTB) links, allowing concurrent access and failover between storage controllers, ensuring data accessibility even in case of a single point failure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If serial storage protocols (Fibre Channel, SAS, SATA) are used with hard disk drives in high availability systems, then system redundancy is achieved, but I/O performance and efficiency are limited

Engineering Contradiction:
Improvesystem redundancyVSAvoidI/O performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the interface protocol from serial storage protocols (Fibre Channel, SAS, SATA) to PCIe parallel protocol, and changes the storage medium from hard disk drives to solid state drives. This parameter change enables simultaneous improvement in both reliability through redundant PCIe paths and productivity through superior I/O performance of SSDs with PCIe interface.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a single PCIe path is used to connect storage controller to PCIe SSD, then device complexity is reduced, but system reliability decreases due to single point of failure

Engineering Contradiction:
Improveinterface structureVSAvoidsystem availability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the single PCIe interface into multiple independent PCIe paths (first PCIe path and second PCIe path) between storage controllers and the PCIe SSD. Each path can operate independently, allowing the system to maintain reliability through redundancy while managing complexity through modular path design with dual port/single port logic controlling each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic path selection and failover capabilities where the dual port/single port logic can switch between first and second PCIe paths based on operational status. This dynamic adaptation allows the system to maintain reliability by activating redundant paths when failures occur, while maintaining simplified single-path operation during normal conditions.

Inventive Principle:
Principle #15Dynamics

3Reliability

If redundant PCIe paths with dual port/single port logic are implemented, then system reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem availabilityVSAvoidinterface structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functionality of multiple PCIe paths and dual port logic into an integrated PCIe SSD device. The dual port/single port logic, first PCIe path, and second PCIe path are combined within a single SSD unit, allowing the system to achieve reliability through redundancy while containing complexity within a unified device rather than requiring complex external switching infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2656228B1Method and apparatus to provide a high availability solid state drive
Publication Date: 2016.03.02 INTEL CORP
  • EP2656228B1 patent drawingFigure 1
  • EP2656228B1 patent drawingFigure 2
  • EP2656228B1 patent drawingFigure 3

AI summary

A method and apparatus to use Solid State Drives (SSD) in a high availability enterprise system is provided. Concurrent redundant paths are provided to the SSD to at least two storage controllers via a serial system bus using a non-storage bus protocol.