Memory Control Chip Write Protection Detection
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Solution Overview
Problem
The existing write protection mechanisms for SD cards, which rely on mechanical switches and external card readers, become ambiguous when high-speed interfaces are introduced, making it difficult for users to differentiate between old and new specifications, and for devices to implement write protection functions compatibly with both.
Innovation Solution
A method and apparatus that utilize a control chip with an interface detection module and write protection detection terminal to selectively initialize transmission interfaces based on protocol support and write protection switch status, allowing host devices to access memory devices through either PCIe or UHS-I/UHS-II/UHS-III protocols, enabling write protection functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a mechanical write protection switch is used in SD cards, then users can directly control write protection status, but the card reader must completely involve the read/write process to implement write protection function
Solution Approach 1:
The patent extracts the write protection detection function from the mechanical switch domain and places it in the electrical detection domain. The control chip detects the write protection switch status through electrical signals (detecting whether the switch is turned on) rather than relying on the card reader to mechanically sense the switch position, thereby reducing the complexity of the card reader's involvement in the read/write process.
Solution Approach 2:
The control chip acts as an intermediary between the mechanical write protection switch and the host device. It detects the switch status and translates it into protocol-specific signals (first protocol for old specifications, second protocol for new specifications), eliminating the need for the card reader to completely involve itself in the read/write process while maintaining user control capability.
2Speed
If high speed interface is introduced in SD cards to improve performance, then data transmission speed is improved, but it becomes hard for users to differentiate between old and new specifications
Solution Approach 1:
The control chip performs interface detection to determine whether the memory device supports the first protocol or requires the second protocol. Based on this detection result and the write protection switch status, the control chip selectively initializes the appropriate transmission interface, providing feedback-based protocol selection that maintains specification differentiation capability while supporting high-speed interfaces.
3Adaptability or versatility
If the control chip selectively initializes different transmission interfaces based on protocol support, then compatibility with both old and new specifications is achieved, but the initialization process becomes more complex
Solution Approach 1:
The control chip performs interface detection and protocol determination during the initialization phase, before actual data transmission begins. By detecting whether the memory device supports the first protocol and determining the appropriate transmission interface in advance, the system prepares the correct configuration beforehand, making the subsequent data transmission process simpler and more efficient.
Data Source
AI summary
A method for performing detection control of a write protection function of a memory device, an associated control chip, and an associated electronic device are provided. The method includes: detecting whether the memory device supports a first protocol to generate an interface detection result; detecting whether a write protection switch of the memory device is turned on to generate a write protection detection result; and according to the interface detection result and the write protection detection result, selectively initializing a transmission interface of a control chip as a first transmission interface conforming to the first protocol or a second transmission interface, to allow a host device to access the memory device through the control chip, wherein the first transmission interface corresponds to a first configuration of the control chip, and the second transmission interface corresponds to a second configuration of the control chip.