Memory Controller Parallel Serial Bus Pin Reduction
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Solution Overview
Problem
The memory-wall effect in high-performance computing and AI systems occurs due to the mismatched scaling of DRAM chips and logic circuits, leading to reduced data transmission rates, and existing solutions like faster data rates or wide buses come with disadvantages such as increased cost, power consumption, and layout complexity.
Innovation Solution
A memory system with a data bus configured for parallel commands and a serial bus for serial commands, utilizing an adaptive conversion circuit to convert input data into 16-bit serial commands, reducing the number of signal pins to less than 45 and maintaining transmission efficiency through multiplexing and time-sharing protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of signal pins is reduced to decrease package cost and layout complexity, then the maximum bandwidth of the bus is reduced
Solution Approach 1:
The patent implements dynamic protocol selection where the memory controller can switch between parallel protocol and serial protocol based on the specific command type and performance requirements. This allows the system to optimize between bandwidth (using parallel for data transfers) and pin reduction (using serial for control signals), resolving the contradiction between reducing pin count and maintaining bandwidth.
Solution Approach 2:
The patent changes the operational parameters of the bus by supporting multiple protocols (parallel and serial) and allowing dynamic adjustment of data width and clock frequency. This enables the system to adapt the bus configuration to different operational modes, achieving both pin reduction and bandwidth maintenance through parameter optimization rather than fixed configuration.
2Speed
If faster data rate is used to transmit data between DRAM chips and logic circuit, then data transmission rate is improved, but cost and noise margin are worsened
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the memory controller can select different clock speeds based on the operational requirements. For control signals, lower frequencies with better noise margins are used, while for data transfers, higher frequencies provide the needed bandwidth. This dynamic adaptation resolves the contradiction between transmission speed and noise immunity.
3Productivity
If wide data bus is used to transmit data between DRAM chips and logic circuit, then data transmission rate is improved, but power consumption and die area are worsened
Solution Approach 1:
The patent segments the bus operations into different protocols: serial protocol for control signals and parallel protocol for data transfers. This segmentation allows the system to use only the necessary bus width for each type of operation, avoiding the power consumption and die area overhead of a permanently wide bus while maintaining high data transmission rates when needed.
4Adaptability or versatility
If more signals are used to connect memory IC to controller IC, then all memory IC functions can be exposed and accessed, but package cost and layout complexity are worsened
Solution Approach 1:
The patent makes the data bus universal by enabling it to carry multiple types of signals through protocol multiplexing. The same physical bus infrastructure supports both parallel data transfers and serial control signals, as well as address and command transmission. This multi-functionality allows full memory IC access capability while using a reduced number of physical pins, thereby reducing layout complexity.
Data Source
AI summary
A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.