Memory Controller Write Queue Logic for Storage Class Memory
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Solution Overview
Problem
Existing non-volatile memory technologies, such as RRAM and PCRAM, face challenges in achieving deterministic write times and low latency, making them less performant compared to DRAM.
Innovation Solution
A memory controller with write queue logic that includes a transfer interface to issue signal components of a write operation to a storage class memory (SCM) device, along with a timer value representing a minimum time interval for subsequent write operations, ensuring deterministic write operations and allowing for pipelined operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If non-volatile memory technologies (RRAM, PCRAM) are used, then manufacturing cost is reduced, but write operation determinism and latency performance deteriorate
Solution Approach 1:
A memory controller is introduced as an intermediary between the host system and the non-volatile memory device. The controller includes write queue logic that buffers write operations and manages their execution timing, thereby determining when writes are actually performed on the memory device. This intermediary layer abstracts the non-deterministic nature of the underlying memory technology from the host system.
Solution Approach 2:
The memory controller performs preliminary actions by pre-managing write operations in a queue before they are executed on the memory device. The controller can prioritize, buffer, and schedule write operations in advance, ensuring that they are executed in a controlled manner that guarantees determinism and meets latency requirements.
2Ease of manufacture
If non-volatile memory technologies (RRAM, PCRAM) are used, then manufacturing cost is reduced, but latency performance deteriorates
Solution Approach 1:
The memory controller enables continuous useful action by maintaining a pipeline of write operations in the write queue. While one write operation is being executed on the memory device, the controller can prepare and queue subsequent write operations, ensuring continuous data flow and minimizing idle time. This pipelining approach reduces overall latency and improves throughput.
Solution Approach 2:
The memory controller dynamically manages write operations based on current system conditions, queue depth, and memory device status. It can adjust the timing and prioritization of write operations in real-time, optimizing latency performance adaptively rather than using fixed timing schemes.
3Quantity of substance
If DRAM devices are scaled down, then storage capacity increases, but capacitive performance for charge storage deteriorates
Solution Approach 1:
The patent replaces expensive, difficult-to-manufacture DRAM devices with cheaper non-volatile memory devices (RRAM, PCRAM, etc.). While these alternative memory technologies have different performance characteristics, they compensate through non-volatility and manufacturing ease, effectively trading the short-lived charge storage capability of DRAM for persistent storage capability.
Data Source
AI summary
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.