Bus Control Circuit Arbitration for Semiconductor Data Transfer
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Solution Overview
Problem
Existing semiconductor devices that arbitrate data transfer between bus masters and bus slaves through a bus often prioritize access based solely on bus master priority, leading to inefficiencies when a high-priority bus master requests access to a busy bus slave, preventing access to non-busy slaves and thereby reducing processing efficiency.
Innovation Solution
A bus control device that obtains access information and busy state information for each bus slave, allowing it to arbitrate access from bus masters to non-busy slaves based on their priority, ensuring that high-priority bus masters access available bus slaves, thereby improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the arbiter transfers data between bus masters and bus slaves according to the priority of each bus master, then the bus access order is controlled and arbitration is simplified, but when a high-priority bus master requests access to a busy bus slave, other bus masters cannot access non-busy slaves, reducing processing efficiency
Solution Approach 1:
The patent segments the bus slave resources into multiple independent groups (first bus slave group and second bus slave group). Each group can be independently accessed by different bus masters simultaneously. This segmentation allows the system to bypass busy slaves in one group by directing high-priority bus masters to available slaves in another group, thereby improving processing efficiency while maintaining simplified arbitration control within each group.
2Reliability
If the arbiter strictly follows bus master priority for data transfer, then priority-based access control is maintained, but available bus slaves cannot be utilized when the preferred slave is busy, leading to wasted resources
Solution Approach 1:
The patent implements dynamic bus master group assignment where bus masters are flexibly assigned to different groups based on real-time slave availability. When a high-priority bus master's preferred slave is busy, the arbiter dynamically redirects the bus master to access available slaves in alternative groups. This dynamic adjustment maintains priority-based control reliability while optimizing resource utilization by preventing idle slaves from remaining unused.
3Stability of the object's composition
If the system waits for high-priority bus masters to complete their transactions before allowing other bus masters to access, then priority ordering is preserved, but overall system throughput decreases due to idle periods
Solution Approach 1:
The patent enables continuous useful action by allowing multiple bus masters to simultaneously access different bus slave groups in parallel. While a high-priority bus master is accessing a slave in the first group, other bus masters can concurrently access slaves in the second group. This eliminates idle waiting periods and maintains system throughput, while the arbitration mechanism within each group preserves stable access ordering and priority control.
Data Source
AI summary
The present invention provides a technique for further improving the processing efficiency in a semiconductor device that arbitrates data transfer between a plurality of bus masters and a plurality of bus slaves.A bus control circuit controls data transfer in an address bus and a data bus between a plurality of bus masters and a plurality of bus slaves. The bus control circuit obtains access information representing the bus slave that each of the bus masters accesses on the basis of address signals output from the bus masters. The bus control circuit obtains busy information representing whether or not each bus slave is in a busy state. In the case where the bus masters compete with each other when accessing a bus slave, the bus control circuit arbitrates access from each bus master to the bus slave that is not in a busy state in accordance with the priority set for each bus master on the basis of the access information and the busy information.