Bonding Circuit for Memory Controller Width Merging
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Solution Overview
Problem
Conventional hard memory controllers are inflexible and costly to support multiple memory data widths, as each data width requires separate hardware, leading to resource wastage and increased design, verification, and layout expenses.
Innovation Solution
An integrated circuit (IC) with a first and second memory controller and a hard logic bonding circuit that coordinates memory control functions, allowing the controllers to function as an N+M bits wide memory controller, enabling flexible configuration for either higher bandwidth or multiple lower bandwidth scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hard memory controllers are designed to support multiple memory data widths, then versatility is improved, but device complexity and cost increase due to requiring separate hardware for each data width combination
Solution Approach 1:
The patent merges multiple memory controllers of different data widths (e.g., two 32-bit controllers, two 64-bit controllers, or one 32-bit and one 64-bit controller) into a single integrated circuit. The bonding circuits enable these controllers to function as a unified memory control unit, allowing the system to support various memory data width configurations without requiring separate hardware for each combination. This consolidation reduces overall hardware complexity while maintaining versatility.
Solution Approach 2:
The integrated memory controller design provides multi-functionality by enabling a single IC to support multiple memory data width configurations. The bonding circuits are designed to coordinate between controllers of different widths, allowing the same hardware to serve multiple purposes (32-bit mode, 64-bit mode, mixed modes) without requiring separate specialized hardware for each configuration, thus achieving universality.
2Adaptability or versatility
If multiple memory controllers of different data widths are used to support various memory configurations, then versatility is improved, but die area increases
Solution Approach 1:
The patent combines multiple memory controllers and their bonding circuits into a single integrated circuit package. By merging what would traditionally require separate ICs into one die, the overall die area is reduced compared to using separate controllers for each data width configuration. The shared bonding circuit infrastructure allows multiple controllers to coexist on a single die without requiring the full resource allocation of separate standalone controllers.
3Reliability
If hard logic bonding circuits are used to coordinate memory controllers, then reliability is improved through fixed logic coordination, but device complexity increases due to additional bonding circuit hardware
Solution Approach 1:
The bonding circuits are designed as self-contained hard logic units that automatically coordinate between memory controllers without requiring external intervention or complex control mechanisms. The bonding circuits inherently manage the coordination tasks (signal routing, timing synchronization, data width matching) through their fixed logic design, eliminating the need for additional complex coordination hardware or software while maintaining high reliability.
Data Source
AI summary
An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.