Accessing Apparatus Clock Frequency Synchronization
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Solution Overview
Problem
Conventional accessing apparatuses in portable electronic devices experience unnecessary power consumption due to the internal clock operating at the highest frequency when the external clock frequency is unknown, leading to inefficient data transmission and reduced battery lifespan.
Innovation Solution
Incorporating a frequency detecting circuit to adjust the internal clock frequency to match the external clock frequency, ensuring optimal data transmission and minimizing power consumption by avoiding buffer overrun or underrun during data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal clock operates at the highest frequency to avoid buffer overrun or underrun, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the internal clock frequency adjustable rather than fixed at the highest level. The clock frequency is dynamically changed based on the detected external clock frequency, allowing the system to adapt between high performance mode (when external clock is fast) and low power mode (when external clock is slow), thus resolving the contradiction between reliability and power consumption
Solution Approach 2:
The patent changes the operating parameter (clock frequency) of the internal clock based on the detected external clock frequency. By detecting the external clock frequency and adjusting the internal clock frequency accordingly, the system optimizes both data transmission reliability and power consumption, avoiding unnecessary high power usage when the external clock operates at lower frequencies
2Use of energy by moving object
If the internal clock frequency is adjusted to match the external clock frequency, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a frequency detecting circuit as an intermediary component between the external clock and the internal clock. This intermediary detects the external clock frequency and provides information to the clock adjusting circuit, which then adjusts the internal clock frequency accordingly. This modular approach reduces overall system complexity by dividing the frequency synchronization function into separate, manageable components
Data Source
AI summary
An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.