Digital Storage TRIZ Cases

Non-volatile resistive memory retains artificial neuron control parameters across power cycles, solving CMOS leakage-induced data loss.

Data path controller eliminates redundant transmission gates by delaying signals, reducing current consumption and chip size while maintaining DDR bandwidth.

Storing parameter codes as offset values in a memory mode register optimizes per-pin operating conditions, reducing signal distortion at high data rates.

An overdrive period control device adjusts timing via a comparison circuit and reference potential.

Central bus-control system coordinates memory access stop periods, suppressing read requests during skew training to optimize bandwidth utilization.

A resistive memory apparatus applies sequential read pulses at varying temperatures to determine storage data states.

Reducing current amplitude during pre-power-down refresh prevents threshold voltage drift from exceeding retention limits.

A data writing method for resistive memory devices performs multiple readings and comparisons to confirm storage states before executing write operations.

Access control circuit differentiates memory cell regions using fuse information to identify defective cells and execute targeted column repairs.

A dual clock FIFO design synchronizes write and read pointers across different clock domains using intermediary circuits to prevent metastability.

Segmented supply domains and a dedicated negative voltage generator maintain stable bit line levels during ultra-low to normal mode transitions.

Precharging digit lines to VCC/2 and controlling coupling rates via isolation switches enables faster sensing while reducing electrical noise susceptibility.

Merging control functions into a single node controller reduces component count, size, and manufacturing cost while preventing pull-down device deterioration.

A memory device uses a mirror circuit to precisely control voltage and current for resistance state setting.

A bipolar resistive switch integrates a heat mitigator to conduct thermal energy away from the switching matrix.

An adaptive error correction technique adjusts scrub rates and ECC parameters based on detected defective memory cells.

Alternating stacked structures with overlapping contacts reduce area constraints, enabling higher memory cell density without increasing device complexity.

A memory array stores trimming information alongside user data to calibrate a sense amplifier for accurate read operations.

A semiconductor memory device uses segmented clocks to control read and write operations independently.

Growth-dominated phase change material prevents crystallization at high temperatures to ensure stable data retention.

Dividing kernels into non zero weight groups with index codes reduces energy consumption and computing time in SRAM based processing units.

Segmented chalcogen layers stabilize switching while suppressing leakage current to enhance semiconductor reliability.

A register clock driver loopback circuit samples chip select signals to verify signal integrity in high-speed memory modules.

Centralized input buffers minimize signal path distance to reduce power consumption in memory devices.

Inverted input signals drive keeper transistors to prevent contention with pull-down devices during evaluation at low voltages.

A memory device refresh controller manages active bank groups to reduce unnecessary power consumption.

A memory interface circuit adjusts signal voltage ranges based on internal impedance to generate accurate input signals.

A memory controller adjusts timing strobe signal delays to synchronize data transfer across multiple memories.

A memory cell uses a ferroelectric capacitor to switch polarization states based on applied potential differences.

Segmented magnetic tracks and buffer domains resolve the trade-off between read speed and device complexity in nonvolatile memory systems.

Merging separate read and write paths into a single structure reduces circuit complexity while maintaining independent latency control.

A wordline assist circuit dynamically alters voltage levels to enhance SRAM cell stability and write performance.

Biasing circuit collapses and restores power to force SRAM bitcells into a desired state, eliminating specialized transistors.

Shared SYNC_PAD pins coordinate die states to prevent output conflicts and burnout in multi-die stacked memory.

Switching resistance at a critical voltage enables multi-bit storage in variable resistors, resolving fabrication complexity and thermal stability issues.

A semiconductor memory apparatus adjusts driving voltage via a control block that senses dummy element resistance.

Control logic circuits skip searches in TCAM sub-arrays with all don't care cells, reducing peak current and stabilizing supply voltage.

A CAS latency setting circuit dynamically adjusts latency values via control signal pulses during test mode.

Canary cells with reduced operating margins detect failure thresholds to dynamically adjust supply voltage, resolving power reliability trade-offs.

A frequency-adjusting circuit determines DRAM refresh rates by comparing current and previous chip temperatures.

A voltage clamper circuit limits current flow to memory cell units, preventing PCM cell melting during read operations.

Adjustable threshold signals in a state machine circuit detect strobe edges, reducing noise interference and false triggering in memory controllers.

Switching components connect capacitors to a voltage source to reduce voltage offsets, improving access accuracy and reducing power consumption.

Precharging bit lines to an intermediate voltage reduces GIDL leakage current while suppressing peak current spikes during resume return.

Data bus inversion encoding reduces current charge and discharge at through substrate vias, lowering power consumption while maintaining memory access speed.

A shift register memory system moves data layers along strings using a control circuit to manage storage and retrieval operations.

A DRAM core architecture uses time-multiplexed I/O bit lines to expand data width without adding physical pins.

A frequency detecting circuit adjusts internal clock speed to match external signals.

A host device multiplexer circuit determines timing relationships between data strobe and internal clock signals to align read data sampling.