Semiconductor Memory Device Clock Segmentation for Power Efficiency
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Solution Overview
Problem
Conventional Static Random Access Memory (SRAM) devices face high power consumption due to the need for a high-frequency source clock to synchronize read and write operations in a burst pattern, leading to inefficient current usage and operational limitations.
Innovation Solution
A semiconductor memory device design that includes a memory block, data output block, write operation signal generation block, and data input block, allowing for simultaneous read and write operations within one cycle of the source clock by using a reference clock lagging behind the source clock by a set time, enabling separate control of data transfer lines for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-frequency source clock is used to synchronize read and write operations in a burst pattern, then operational reliability is improved, but power consumption increases
Solution Approach 1:
The patent segments the clock signal into two distinct clocks: a source clock for read operations and a lower-frequency reference clock for write operations. This segmentation allows each operation type to use the minimum necessary clock frequency, improving power efficiency while maintaining reliability for both read and write operations in burst patterns.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal used for write operations. Instead of using a high-frequency source clock for both read and write operations, the system uses a lower-frequency reference clock specifically for write operations, thereby reducing power consumption while maintaining operational reliability.
2Device complexity
If a single source clock is used for both read and write operations, then device complexity is reduced, but operational efficiency deteriorates
Solution Approach 1:
The patent introduces a write operation signal generation block that segments the clock control function. This block generates write operation signals based on the reference clock and operation selection signals, enabling independent control of write operations without significantly increasing overall device complexity while improving operational efficiency.
Solution Approach 2:
The patent introduces a write operation signal generation block as an intermediary component that translates the reference clock and operation selection signals into precise write operation timing signals. This intermediary enables efficient coordination of read and write operations without requiring a completely complex dual-clock architecture.
3Stability of the object's composition
If read and write operations are performed in separate clock cycles, then operational stability is improved, but productivity decreases
Solution Approach 1:
The patent implements periodic action by using the reference clock to periodically enable write operations at specific timing intervals. The write operation signal generation block generates write enable signals at regular periods based on the reference clock, allowing stable and predictable write operations to occur periodically within the burst pattern without disrupting overall operational stability.
Solution Approach 2:
The patent applies preliminary action by generating write operation signals in advance based on the reference clock before the actual write operation occurs. This allows the system to prepare write timing ahead of time, ensuring stable operation while maintaining high productivity through efficient burst pattern execution.
Data Source
AI summary
A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal.