DRAM Core Architecture with Wide I/Os and Time-Multiplexed Bit Lines
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Solution Overview
Problem
Traditional DRAM architectures face limitations in bandwidth due to the lack of additional I/O bit lines, leading to high power consumption and frequent refreshing, and are not capable of reading out more data simultaneously effectively.
Innovation Solution
A new DRAM architecture is proposed where the traditional location of I/Os and column selects are swapped, converting an 8-bit I/O structure to a 64-bit I/O structure, with interweaved power lines and time-sharing of I/O bit lines to reduce the number of lines and redistribute peak current across multiple operations, thereby enhancing memory performance for high-definition displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DRAM architecture with limited I/O bit lines is used, then device complexity is reduced, but bandwidth and data readout capability are limited
Solution Approach 1:
The patent segments the I/O operations by dividing the 64 I/O bit lines into multiple groups that can be time-multiplexed. This allows the system to handle larger data widths by organizing I/O operations in sequential segments rather than requiring all I/O lines to be active simultaneously, thus improving bandwidth while controlling device complexity.
Solution Approach 2:
The patent introduces a time dimension to the I/O architecture through time-multiplexing. By alternating between different sets of I/O bit lines across multiple time slots, the system effectively increases the bandwidth capability without proportionally increasing the physical number of I/O lines, resolving the contradiction between productivity and device complexity.
2Productivity
If more I/O bit lines are added to increase bandwidth, then data readout capability is improved, but power consumption increases due to more lines
Solution Approach 1:
The patent implements periodic action by time-multiplexing the I/O bit lines, where different sets of lines are activated in alternating time slots. This periodic activation allows the system to achieve high data readout capability using a manageable number of physical lines, as each line is used intensively during its allocated time slot but remains inactive otherwise, thereby reducing overall power consumption compared to having all lines continuously active.
Solution Approach 2:
The system dynamically switches between different sets of I/O bit lines based on the current operation phase. This dynamic reconfiguration allows the memory controller to activate only the necessary subset of I/O lines at any given time, optimizing the balance between data readout capability and power consumption by avoiding the continuous activation of all possible I/O lines.
3Ease of manufacture
If traditional DRAM architecture is used, then fabrication is simpler, but frequent refreshing is required due to current leakage
Solution Approach 1:
The patent enhances the functionality of the DRAM architecture by integrating wide I/O capabilities into the traditional simple DRAM cell structure. The multi-functional design allows the same basic cell structure to support both simple fabrication processes and improved data access patterns that reduce refreshing requirements, thereby maintaining ease of manufacture while reducing time loss from frequent refreshing.
4Productivity
If I/O and column select locations are swapped to create wide I/O structure, then bandwidth is increased, but manufacturing complexity increases
Solution Approach 1:
The patent applies inversion by swapping the traditional locations of I/O and column select structures. Instead of having column selects at the edge and I/O in the center, the design places I/O structures at the edge and column selects in the center. This inverted arrangement enables wide I/O bandwidth while maintaining a systematic layout that can be manufactured using standard processes, thus resolving the contradiction between productivity and ease of manufacture.
Data Source
AI summary
A dynamic random-access memory (DRAM) for use with a display includes a plurality of capacitive elements coupled to store one or more bits of data, and a plurality of switches where at least one individual switch in the plurality of switches is coupled to an individual capacitive element in the plurality of capacitive elements. A plurality of input/output (I/O) bit lines including 32 or more input/output bit lines is coupled to read out the data from the plurality of capacitive elements. A plurality of column select lines is coupled to enable readout of the plurality of capacitive elements.