Semiconductor Memory Device Overlapping Contact Regions
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face limitations in increasing their degree of integration due to large contact regions, which restrict the further enhancement of memory cell stacking density.
Innovation Solution
The semiconductor memory device employs a configuration where first and second stacked structures with overlapping contact regions are arranged alternately, with lines coupled in common to these contact regions, reducing the total contact area and enhancing integration by efficient arrangement of drain selection lines, bit lines, and voltage supply lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three-dimensional structures to increase integration density, then storage capacity is improved, but contact region area increases limiting further integration enhancement
Solution Approach 1:
The patent transitions from two-dimensional contact regions to three-dimensional vertically-aligned contact regions. Multiple contact regions are stacked in the vertical direction and aligned to overlap when viewed from above, effectively utilizing the third dimension to reduce the planar contact area while maintaining electrical connections to multiple memory layers.
Solution Approach 2:
The patent implements a nested structure where multiple contact regions are contained within a reduced planar footprint. The vertically-aligned contact regions are positioned such that their projections overlap on the substrate plane, creating a compact arrangement where contact regions for different memory layers are nested in the vertical dimension.
2Quantity of substance
If more stacked structures are added to increase memory capacity, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent implements shared bit lines that serve multiple memory stacks simultaneously. A single bit line is coupled to multiple contact regions across different stacked structures, allowing one signal line to perform multiple functions and access memory cells in several stacks, thereby reducing the total number of bit lines required.
Solution Approach 2:
The patent merges the control and signal routing for multiple stacked structures by using common bit lines and control lines. Instead of providing separate routing for each stack, the invention combines the connections so that a single bit line can interface with multiple stacks through vertically-aligned contact regions.
Data Source
AI summary
A semiconductor memory device includes a plurality of first stacked structures including a plurality of first material layers at ends of which first contact regions are defined, a plurality of second stacked structures including a plurality of second material layers, wherein second contact regions are defined at ends of the second material layers and arranged between the first stacked structures so that the first contact regions and the second contact regions overlap each other, and a plurality of lines coupled in common to the first contact regions and the second contact regions.