Semiconductor Access Control for Skew Training
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Solution Overview
Problem
Existing semiconductor devices do not effectively manage access control in consideration of skew adjustment during memory operations, leading to potential disruptions in real-time data processing due to the time-consuming nature of skew adjustment processes, which can impact memory bandwidth and system responsiveness.
Innovation Solution
A semiconductor device with an access control unit that suppresses read requests during skew training periods, allowing for improved real-time response by prioritizing write requests and managing access rights through a central bus-control system that recognizes and coordinates memory access stop periods, including those caused by write training operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If skew adjustment is performed in memory, then timing precision between clock and data signals is improved, but memory access is stopped for a relatively long time
Solution Approach 1:
The system performs skew adjustment in advance during initialization or idle periods before normal memory operations begin. By completing the timing calibration beforehand, the system ensures that subsequent memory accesses can proceed without interruption, thus achieving precise timing without sacrificing operational time.
2Manufacturing precision
If access control is not performed during training periods, then skew adjustment can be completed, but real-time data processing is disrupted
Solution Approach 1:
The system segments memory access into distinct phases: training periods for skew adjustment and operational periods for data processing. During training, access control units suppress non-critical access requests while allowing essential operations to continue. This segmentation enables skew adjustment without completely halting real-time processing capabilities.
Solution Approach 2:
The system implements periodic skew adjustment at predetermined intervals or triggers rather than continuously. Access control units are configured to temporarily suppress access requests only during these periodic training windows, while maintaining normal processing between intervals. This periodic approach balances the need for timing precision with continuous productivity.
3Productivity
If read requests are not suppressed during training, then memory bandwidth is utilized, but training effectiveness is reduced
Solution Approach 1:
The access control unit applies different quality levels of access control to different types of requests during training. Write requests, which are more critical for training effectiveness, receive higher priority and are less likely to be suppressed. Read requests, which are less critical, are more readily suppressed during training periods. This local differentiation maintains training effectiveness while preserving essential memory bandwidth utilization.
Data Source
AI summary
Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.