Voltage Clamper Circuit for Cross-Point Memory Cell Protection
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Solution Overview
Problem
The fast-fast corner cells in cross-point memory arrays, such as phase change memory (PCM), are prone to disturbance during read or set operations due to high cell currents, which can lead to the PCM cell being melted, as the PMOS transistor in the word line switch fails to turn off effectively.
Innovation Solution
A voltage clamper circuit, comprising NMOS or PMOS transistors, is integrated into the word line or bit line switch circuits to limit the current flowing to the memory cell units, clamping the voltage and preventing excessive current flow that could melt the PCM cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bit line voltage is applied to select memory cells, then the memory cell can be accessed for read or write operations, but the fast-fast corner cells are disturbed and reset due to excessive current flow
Solution Approach 1:
A voltage clamper circuit is introduced as an intermediary component between the bit line and the memory cell. This clamper circuit includes a capacitor connected in parallel with the bit line, which acts as a voltage limiter and current regulator. The capacitor charges to a predetermined voltage level and prevents excessive voltage spikes from reaching the memory cell, thereby protecting the cell from disturbance while still allowing proper selection operations to function.
2Ease of operation
If the PMOS transistor in the word line switch is used to control current, then the word line can be selected, but the PMOS transistor fails to turn off effectively due to voltage coupling
Solution Approach 1:
The voltage clamper circuit serves as an intermediary that decouples the voltage coupling between the bit line and the word line. By limiting the voltage at the bit line to a predetermined level, the clamper prevents the voltage spike from coupling through the OTS to the word line, which in turn allows the PMOS transistor to turn off effectively without leakage current.
Solution Approach 2:
The voltage clamper changes the voltage parameter at the bit line by limiting it to a predetermined maximum value. This parameter change ensures that even when the OTS is fully conductive, the voltage does not exceed the threshold required to keep the PMOS transistor properly controlled, eliminating the off-PMOS leak condition.
3Device complexity
If no voltage clamping is applied, then the circuit remains simple, but the cell current becomes excessive and melts the PCM cell
Solution Approach 1:
The voltage clamper circuit is a simple intermediary structure consisting of a capacitor connected in parallel with the bit line. This straightforward configuration provides voltage limiting and current regulation functions that prevent excessive current from reaching the PCM cell, thereby preventing cell melting without significantly increasing circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the voltage clamper circuit reduces cell current during read and set operations, effectively minimizing the disturbance of fast-fast corner cells and preventing PCM cell melting by ensuring the PMOS transistor turns off correctly.
Implementation Method 1
a voltage clamper, coupled to the pass gate and applied with a clamp voltage for clamping a voltage at a node between the pass gate and the voltage clamper or for limiting a current flowing to the memory cell unit
Data Source
AI summary
A memory array is provided and including a plurality of bit lines and a plurality word lines; a plurality of memory cell units, arranged at cross points of the plurality of bit lines and the plurality of word lines; a bit line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of bit lines; a word line switch circuit, coupled to the plurality of memory cell units and being operated to select one of the plurality of word lines; and a voltage clamper circuit, provided in at least one of the word line switch circuit and the bit line switch circuit.