DRAM Refresh Controller with Selective Bank Group Activation
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Solution Overview
Problem
Mobile electronic devices require frequent refresh operations for DRAM to counter charge leakage, leading to high refresh currents, which are wasteful and inefficient, especially when not all memory areas are actively used.
Innovation Solution
A memory device and system that utilize a refresh controller to selectively refresh only the memory areas where programs are executed, using a flag bit system to enable or disable refresh operations based on program allocation, thereby reducing unnecessary refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all memory areas, then data integrity is maintained, but refresh current consumption increases
Solution Approach 1:
The memory device divides the memory cell array into multiple bank groups, where each bank group can be independently controlled for refresh operations. This segmentation allows the refresh function to selectively operate on only the necessary bank groups rather than the entire memory array, thereby maintaining data integrity in active areas while reducing refresh current consumption in inactive areas.
Solution Approach 2:
The refresh control mechanism applies different refresh behaviors to different regions of the memory device based on their usage status. Active bank groups receive normal refresh operations to maintain data integrity, while inactive bank groups have refresh operations disabled or reduced, optimizing energy consumption by matching refresh activity to actual data usage patterns.
2Reliability
If refresh operations are performed frequently, then charge leakage is compensated, but power consumption increases
Solution Approach 1:
The refresh control logic dynamically adjusts the refresh operation frequency and scope based on real-time detection of memory access patterns. When memory areas are actively accessed, refresh operations continue at normal frequency to maintain charge retention. When areas become inactive, the refresh frequency is reduced or operations are disabled, thereby reducing power consumption while maintaining reliability for active data.
Solution Approach 2:
The memory device includes an internal refresh control mechanism that automatically monitors and manages refresh operations without requiring external controller intervention. The refresh control logic detects inactive bank groups and autonomously disables or reduces refresh operations in those areas, enabling the device to self-optimize its power consumption based on actual usage patterns while maintaining data integrity where needed.
Data Source
AI summary
A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.