SRAM Bit Line Precharge for Leakage and Peak Current Control
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Solution Overview
Problem
In semiconductor storage devices, particularly SRAM, the leakage current to the substrate of an access transistor through bit lines due to GIDL (Gate Induced Drain Leakage) is significant, and existing techniques fail to effectively reduce this current at room temperature, while setting bit lines to floating during resume standby mode increases peak current and can cause voltage drops, leading to reliability defects like electromigration.
Innovation Solution
A semiconductor storage device configuration that includes an SRAM memory cell, an I/O circuit with a write driver, sense amplifier, and an operating mode control circuit, which switches the operating mode and precharges bit lines with a smaller driving force during mode transitions, keeping bit lines in a floating state during resume standby to minimize leakage current and manage peak current during mode changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If bit lines are set to floating state during resume standby to reduce GIDL leakage current, then leakage current is reduced, but peak current increases significantly during resume return
Solution Approach 1:
The patent applies preliminary action by precharging bit lines to a intermediate voltage level (e.g., VDD/2 or VDD-|Vth|) before returning from resume standby mode. This preliminary precharge reduces the voltage difference that needs to be charged during the transition, thereby reducing the peak current while maintaining the floating state benefit for leakage reduction.
Solution Approach 2:
The patent changes the voltage parameter of bit lines during mode transition. Instead of charging from VSS to VDD directly (full voltage swing), the bit lines are first brought to an intermediate voltage level during the floating state, and then charged to the final VDD level. This parameter change reduces the charging current peak during resume return.
2Reliability
If precharge transistor charges all bit lines simultaneously during resume return, then bit lines are restored to operational state, but instantaneous voltage drop occurs causing reliability defects
Solution Approach 1:
The patent segments the bit line charging process into multiple phases or groups. Instead of charging all bit lines simultaneously with one large precharge transistor, the bit lines are divided into multiple groups that are charged sequentially or in parallel with smaller transistors. This segmentation distributes the current load and prevents instantaneous voltage drops.
Solution Approach 2:
The patent introduces dynamic control of the precharge process by using control signals to enable precharge transistors at different times for different bit line groups. This dynamic approach allows the system to manage peak current by controlling the timing and sequence of bit line charging, preventing simultaneous charging that causes voltage drops.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current and suppresses peak current during mode switching, preventing voltage drops and reliability defects such as electromigration, while effectively managing GIDL and channel leakage currents.
Implementation Method 1
a leakage current to the substrate of an access transistor through the bit lines is large due to GIDL (Gate Induced Drain Leakage)
Data Source
AI summary
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.