Semiconductor Layered Device Data Bus TSV Redundancy
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Solution Overview
Problem
3D memory devices, such as High Bandwidth Memory (HBM), face issues with high power consumption due to defects in through substrate vias (TSVs) connections, which can lead to reduced device yield and increased power usage during data transmission.
Innovation Solution
The implementation of a domino circuit with redundant TSVs and data bus inversion (DBI) encoding and decoding mechanisms to manage data transmission efficiently, detouring defective vias and reducing current consumption by using a redundancy enable signal to activate redundant TSVs for data detouring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission is performed through TSVs in 3D memory devices, then memory access speed and bandwidth are improved, but power consumption increases due to current charge and discharge at the TSVs
Solution Approach 1:
The patent applies data bus inversion (DBI) encoding to change the electrical parameters of data transmission. By inverting data bits based on transition counting, the system reduces the number of simultaneous transitions on the data bus, thereby reducing current charge and discharge at TSVs and lowering power consumption while maintaining high-speed memory access
2Use of energy by moving object
If data bus inversion is applied to reduce current consumption, then power consumption is reduced, but device complexity increases due to additional DBI bits and encoding/decoding circuits
Solution Approach 1:
The patent integrates DBI encoding and decoding functions into existing memory controller and memory device architectures. The DBI encoder in the memory controller and DBI decoder in the memory device share the same functional blocks used for normal data transmission, allowing the power management feature to be added without proportionally increasing overall device complexity
3Reliability
If redundant TSVs are provided to handle defective connections, then device yield is improved, but the number of TSVs and device complexity increase
Solution Approach 1:
The patent incorporates redundant TSVs and domino circuits into the memory device architecture during manufacturing. The redundancy enable signal allows the system to pre-configured backup pathways to be activated only when needed, based on defect detection, thereby improving device yield without requiring all redundant structures to be actively managed during normal operation
Data Source
AI summary
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array.