Centralized Command Address Input Buffer Power Reduction
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Solution Overview
Problem
In synchronous semiconductor memory devices, the delay circuitry used to synchronize command and address signals with latch clocking signals consumes unnecessary power when the memory device is unselected, as it continues to process logical state changes even when the chip select signal is disabled.
Innovation Solution
Implementing logic circuitry and centralized input buffers that selectively enable only a subset of delay circuitry to consume power, and optimizing the input buffer design to reduce power consumption by minimizing the physical distance between the chip select and command/address signal paths, while using a direct path architecture for clock signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay circuitry is provided to synchronize CA signals with latch clocking signals, then timing synchronization is improved, but power consumption increases during disabled state
Solution Approach 1:
The delay circuitry is segmented into multiple delay blocks that can be selectively enabled. The first delay blocks are enabled only when the chip select signal is active, while second delay blocks are enabled based on the state of the first delay blocks. This segmentation allows the system to maintain timing synchronization during active operations while disabling unnecessary delay circuitry during disabled states, thereby reducing power consumption.
Solution Approach 2:
The delay circuitry is made dynamic through control logic that adjusts its operation based on the chip select signal state. The control logic dynamically enables or disables specific delay blocks according to whether the memory device is in an active or disabled state. This dynamic adjustment ensures that delay circuitry consumes power only when needed for timing synchronization, eliminating unnecessary power consumption during disabled periods.
2Use of energy by moving object
If centralized input buffers are implemented, then power consumption is reduced by minimizing signal path distance, but device layout complexity increases
Solution Approach 1:
The input buffers are merged into a centralized location on the memory device, combining the functionality of multiple input buffers into a single consolidated structure. This merging minimizes the physical distance between the chip select signal path and the command/address signal paths, reducing signal skew and power consumption. The centralized design integrates delay blocks and control logic into a compact arrangement that achieves multiple objectives simultaneously.
Data Source
AI summary
An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.