Semiconductor Memory Column Repair via Fuse-Based Region Access
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Solution Overview
Problem
Semiconductor chips, particularly DRAMs, face increased defect introduction during manufacturing due to size reduction, leading to potential operational errors if defects are not detected during initial testing.
Innovation Solution
A semiconductor memory device with a memory cell array comprising a first and second cell region, accessed differently by an access control circuit based on fuse information and an access address, allowing for flexible column repair operations by simultaneously activating word-lines to identify and repair defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor chips are reduced in size through precision manufacturing processes, then manufacturing precision is improved, but the likelihood of introducing defects increases
Solution Approach 1:
The patent performs preliminary defect detection through initial testing processes before chip operations begin. Defective portions are identified and marked during manufacturing testing, enabling proactive repair planning before the chips enter service, thus preventing operational failures while maintaining small chip sizes
Solution Approach 2:
The patent discards defective memory cells identified through testing and recovers the overall chip functionality by performing repairs. Redundant good cells are activated to replace defective ones, allowing the chip to be salvaged and continue operation despite manufacturing defects introduced during size reduction
2Reliability
If initial testing processes are performed to detect defects, then reliability is improved, but productivity is reduced due to additional testing time
Solution Approach 1:
The patent extracts only the essential testing functions needed to identify defective cells, separating critical defect detection from comprehensive full-characterization testing. This selective approach maintains reliability by catching major defects while reducing overall testing time and improving productivity
Solution Approach 2:
The patent performs partial testing focused on detecting defective memory cells rather than exhaustive testing of all chip functions. This partial action approach identifies sufficient defects to enable repair operations while avoiding the productivity loss associated with complete testing of every chip parameter
3Reliability
If column repair operations are performed to fix defective cells, then reliability is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent segments the memory cell array into multiple regions and divides repair operations into discrete column-based units. By organizing repair controls at the column level rather than requiring full-array control, the system achieves reliable defect repair while managing complexity through modular, segmented control structures
Solution Approach 2:
The patent implements dynamic repair control where the access control circuit adaptively determines whether to perform normal access or repair operations based on real-time address comparison with stored defective cell addresses. This dynamic approach enables reliable repair functionality while keeping the control circuit relatively simple by only activating repair modes when actually needed
Data Source
AI summary
A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.