Memory Interface Circuit Voltage Adjustment for Power Reduction
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Solution Overview
Problem
Existing memory interface circuits in storage devices with volatile memory modules consume high power due to the presence of termination resistors, which are necessary for maintaining signal quality but increase power consumption.
Innovation Solution
A memory control circuit unit with a memory interface circuit that adjusts voltage values of signals from volatile memory based on internal impedance, using a combination of first and second impedance components to operate in different modes, reducing power consumption while maintaining signal correctness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a termination resistor is used in the memory interface circuit to maintain signal quality, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the impedance component switchable between different states (activated and non-activated). The memory interface circuit dynamically adjusts its impedance configuration based on operational requirements, allowing it to maintain signal quality when needed while reducing power consumption during normal operation. This is achieved through a switchable impedance component that can be activated or deactivated according to the signaling protocol being used.
Solution Approach 2:
The patent changes the impedance parameter of the memory interface circuit by introducing a switchable impedance component. This component can alter the electrical characteristics of the interface circuit, effectively changing from a high-power termination state to a low-power high-impedance state. The parameter change allows the circuit to adapt to different operational modes, maintaining signal integrity when required while minimizing power consumption during standard operations.
2Reliability
If the memory interface circuit operates in high-power mode with termination resistor, then signal reception reliability is improved, but power consumption increases
Solution Approach 1:
The memory interface circuit employs dynamic operation modes where the impedance component can be switched between activated and non-activated states. This dynamic behavior allows the circuit to transition between high-power reliable reception mode and low-power standby mode, optimizing the balance between reliability and energy consumption based on actual operational needs.
Solution Approach 2:
The circuit changes its operational parameters by adjusting the impedance state through the switchable component. When the impedance component is activated, the circuit operates with modified electrical characteristics that enhance signal reception reliability. When deactivated, it returns to standard operation with lower power consumption, thus dynamically adjusting parameters to meet different operational requirements.
3Use of energy by moving object
If the memory interface circuit uses switchable impedance component to reduce power consumption, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the impedance function into a separate switchable component rather than having a fixed termination resistor. This segmentation allows the impedance control function to be independently managed and switched, reducing its impact on the overall circuit while maintaining its benefits. The switchable impedance component is integrated into the existing memory interface circuit architecture, adding minimal complexity while enabling power savings.
Data Source
AI summary
A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.