DRAM Refresh Frequency Adjustment via Temperature Comparison
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Solution Overview
Problem
Conventional electronic memory systems face shutdown issues due to temperature differences among DRAM chips, leading to a fixed refresh frequency that results in power consumption problems when temperatures decrease.
Innovation Solution
A frequency-adjusting circuit with a temperature-sensing module and computing module that determines a refresh frequency for DRAM chips by comparing current and previous temperatures, adjusting the frequency based on temperature differences to maintain optimal operation without excessive power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the controller reads temperatures of multiple DRAM chips to determine refresh frequency, then the refresh operation can be optimized for each chip, but the system shuts down due to error because the read temperatures are different from each other
Solution Approach 1:
The patent introduces a buffer chip as an intermediary between the controller and multiple DRAM chips. The buffer chip reads temperatures from individual DRAM chips and processes them separately, preventing direct temperature comparison conflicts that cause system shutdown. This mediator handles the temperature data from different chips independently and generates appropriate refresh commands for each chip based on its specific temperature, thus maintaining system stability while enabling optimized refresh operations.
2Reliability
If the temperatures of all DRAM chips are maintained at a preset temperature, then system shutdown problem is solved, but the fixed refresh frequency leads to power consumption problem when temperatures decrease
Solution Approach 1:
The patent implements dynamic refresh frequency adjustment for each DRAM chip based on its actual temperature. Instead of maintaining a fixed preset temperature for all chips, the system continuously monitors individual chip temperatures and adjusts refresh frequencies dynamically. When a chip's temperature decreases, its refresh frequency is reduced accordingly, preventing unnecessary power consumption while maintaining system stability through continuous adaptation to changing thermal conditions.
Solution Approach 2:
The patent applies different refresh frequencies to different DRAM chips based on their individual temperature characteristics. Each chip receives a customized refresh strategy tailored to its specific thermal state rather than a uniform approach. This localized optimization allows chips operating at lower temperatures to consume less power through reduced refresh rates, while chips at higher temperatures maintain appropriate refresh frequencies for stability.
3Device complexity
If a fixed refresh frequency is used for all DRAM chips, then system operation is simplified, but power consumption increases when temperatures of DRAM chips decrease
Solution Approach 1:
The patent transitions from static fixed refresh frequency to dynamic adaptive refresh frequency for each DRAM chip. The system automatically adjusts refresh rates based on real-time temperature monitoring, enabling simplified operation without manual intervention while reducing power consumption when temperatures decrease. The dynamic adjustment occurs transparently through the buffer chip's temperature-based control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively determines a representative temperature for DRAM chips, preventing system shutdown while optimizing refresh frequency to alleviate power consumption issues, thus enhancing the performance and reliability of electronic memory systems.
Implementation Method 1
a temperature-sensing module (11) configured to measure temperatures of a plurality of DRAM chips (9)
Data Source
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AI summary
The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. The computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.