Negative Bit Line Control for Dual-Rail SRAM Voltage Stability
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Solution Overview
Problem
Dual-rail SRAMs face challenges in maintaining stable negative voltage levels during mode switching between ultra-low and normal supply voltages, affecting memory access time and increasing design complexity.
Innovation Solution
A memory device with a negative-bit-line timing control circuit and a negative voltage provider, both supplied by a higher supply voltage, to stabilize the negative voltage level across mode transitions, and using separate supply voltages for different components to manage power consumption and access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the SRAM uses ultra-low supply voltage to reduce power consumption and chip area, then power consumption and chip area are reduced, but memory access time is greatly affected
Solution Approach 1:
The patent divides the SRAM system into two separate supply voltage domains: a first supply voltage (VCC) for the memory array and a second supply voltage (VIO) for the IO circuits and control logic. This segmentation allows the memory array to operate at ultra-low voltage for reduced power consumption while the IO circuits operate at higher voltage for fast access speeds, resolving the contradiction between power consumption and access speed.
2Reliability
If the SRAM applies negative voltage to bit line to improve write ability, then write ability is improved, but negative voltage level becomes unstable during supply voltage switching
Solution Approach 1:
The patent introduces a negative voltage generator circuit as an intermediary component that receives the unstable negative voltage from the bit line and generates a stable negative voltage (e.g., -2.5V) for the write driver. This intermediary circuit decouples the unstable negative voltage from the write driver, ensuring stable write ability regardless of supply voltage switching.
Solution Approach 2:
The patent changes the parameter of negative voltage generation by using a dedicated negative voltage generator that references a stable voltage source rather than deriving it from the unstable bit line voltage. This parameter change ensures that the negative voltage level remains stable (-2.5V) even when supply voltages switch between ultra-low and normal modes.
3Adaptability or versatility
If the SRAM switches between ultra-low and normal supply voltages to adapt to different operating modes, then adaptability is improved, but design complexity increases
Solution Approach 1:
The patent segments the SRAM into two independent voltage domains with separate supply circuits. The memory array operates at VCC (ultra-low voltage) while IO circuits operate at VIO (normal voltage). This segmentation enables mode adaptability through voltage switching without requiring complex reconfiguration of the entire SRAM, thus reducing design complexity.
Solution Approach 2:
The patent implements a universal voltage selection mechanism where the same SRAM structure can operate in multiple modes (ultra-low voltage mode for power saving, normal voltage mode for performance) by simply switching the supply voltages. This multi-functionality is achieved without adding complex mode-specific circuitry, maintaining design simplicity.
Data Source
AI summary
The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.