SRAM CIM Processing Unit Hardware Software Co-Compression

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Solution Overview

Problem

The limited capacity of static random access memory (SRAM) computing-in-memory-based processing units restricts the amount of data that can be computed in a single operation, leading to increased computing time and energy consumption.

Innovation Solution

A hardware/software co-compressed computing method that divides input feature data into weight groups, assigns index codes to non-zero weight groups, and performs inner product calculations in the SRAM CIM-based processing unit, filtering out non-essential data to increase computing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the capacity of SRAM CIM-based processing unit is limited, then the computing amount in a single time is restricted, but expanding the number of processing units increases device complexity

Engineering Contradiction:
Improvecomputing amount in single timeVSAvoidnumber of processing units
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the feature data group into multiple batches and segments the weight groups into non-zero and zero groups. By processing different batches of data through the same SRAM CIM-based processing unit sequentially, the system achieves higher total computing throughput without increasing the number of processing units, thus resolving the contradiction between productivity and device complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of weight groups by identifying and separating non-zero weight groups from zero weight groups. This parameter change allows the system to process only meaningful data (non-zero weights) in each batch, increasing the effective computing amount per single time without requiring additional processing units

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If data is computed in batches due to SRAM capacity limitation, then computing time increases, but processing all data through full kernels increases energy consumption

Engineering Contradiction:
Improvecomputing timeVSAvoidenergy consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent extracts and identifies non-zero weight groups from the full set of weight groups using sparsity-aware computing methods. By taking out only the non-zero weight groups for processing and skipping zero weight groups, the system reduces the number of computations required per batch, thereby reducing both computing time and energy consumption simultaneously

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of processing all weight groups (excessive action), the patent applies partial action by processing only the non-zero weight groups. This partial processing approach reduces the computing workload in each batch, leading to reduced computing time and lower energy consumption while maintaining computational accuracy

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12260906B2Hardware/software co-compressed computing method and system for static random access memory computing-in-memory-based processing unit
Publication Date: 2025.03.25 NATIONAL TSING HUA UNIVERSITY
  • US12260906B2 patent drawing
  • US12260906B2 patent drawing
  • US12260906B2 patent drawing

AI summary

A hardware/software co-compressed computing method for a static random access memory (SRAM) computing-in-memory-based (CIM-based) processing unit includes performing a data dividing step, a sparsity step, an address assigning step and a hardware decoding and calculating step. The data dividing step is performed to divide a plurality of kernels into a plurality of weight groups. The sparsity step includes performing a weight setting step. The weight setting step is performed to set each of the weight groups to one of a zero weight group and a non-zero weight group. The address assigning step is performed to assign a plurality of index codes to a plurality of the non-zero weight groups, respectively. The hardware decoding and calculating step is performed to execute an inner product to the non-zero weight groups and the input feature data group corresponding to the non-zero weight groups to generate the output feature data group.