Memory Mode Register Offset Parameter Codes for Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed memory devices face challenges in accurately capturing signals at high clock frequencies due to signal distortions and noise, leading to suboptimal signal integrity, especially as data rates increase.
Innovation Solution
The implementation of a memory device with a mode register set that stores both global and per-pin operation parameter codes, allowing for precise setting of operating conditions for signal pins, including reference voltage and decision feedback equalizer settings, to optimize signal integrity by adjusting operating conditions based on the specific characteristics of each signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high clock frequency is used to support high data rates, then data transmission speed is improved, but signal integrity deteriorates due to signal distortions and noise
Solution Approach 1:
The patent applies local quality by storing separate per-pin operation parameter codes in the mode register set for each signal pin, allowing individual optimization of operating conditions (such as reference voltage and decision feedback equalizer settings) for each specific signal line based on its unique physical characteristics, thereby improving signal integrity at high data rates without sacrificing transmission speed
2Reliability
If per-pin operation parameter codes are stored in mode register set, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the operation parameters into global parameters (common to all pins) and per-pin parameters (specific to each signal pin). The mode register set is structured to store both global operation parameter codes and per-pin operation parameter codes separately, allowing the system to achieve pin-specific optimization while maintaining a manageable organizational structure that reduces operational complexity
3Adaptability or versatility
If multiple parameter codes are stored for one operation parameter, then adaptability to different signal characteristics is improved, but storage space requirement increases
Solution Approach 1:
The patent stores multiple parameter codes (global and per-pin) for one operation parameter in the mode register set, enabling the system to adapt to different signal characteristics by selecting appropriate codes based on the specific pin being configured. This segmented storage approach provides adaptability while organizing data efficiently to minimize storage space consumption
Data Source
AI summary
Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.